28 #define QQQdialect MPLABX 42 #undef QQQMULTIPROCESSEXH 45 #define qqqMaxBranchDepth 20 46 #define QQQstructbitmap 58 #undef QQQTEMPLATEONLY 60 #define QQQUPLOADATEND 62 #undef QQQASHLINGVITRA 64 #define qqqbitmapint unsigned int 66 #undef QQQTIC2XSERIALIO 68 #undef QQQCOMPRESSED_EXH 75 #define statusst_58zzopen zzopen 77 #define statusst_58zqqzqz1 zqqzqz1 80 #define FILEPOINT FILE * f, 81 #if !defined(QQQTEMPLATEONLY) && !defined(FILE) && !defined(QQQNOSTDIO) 97 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.h" 98 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.h" 101 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.c" 102 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.c" 110 #if defined(QQQstructbitmap) && defined(QQQSINGLEFILE) 111 #ifndef LDRA_VOID_FUNC 112 #define LDRA_VOID_FUNC 115 #if defined(QQQMAINFL) 138 #ifdef QQQ_KEEPCOMMENTS 146 #if !defined(QQQSUPPRESS_UNDEF) 152 #undef QQQHITMAP_STORAGE 154 #define qqnull_params void 155 #define QQQ_PROTOTYPE_DEF 157 #undef QQ_ANSI_PROTOTYPE 159 #define QQ_ANSI_PROTOTYPE 1 162 #define QQ_ANSI_PROTOTYPE 1 168 #define ELEMENT(N) qqqbitmapint element##N; 170 #include "statusst_58zbelem.def" 174 #define ELEMENT(N) 0, 176 #include "statusst_58zbelem.def" 438 const uint8_t Bytes [] ) ;
469 const uint8_t Bytes [] ) ;
559 #define FIFO_RX_SIZE 7 560 #define FIFO_TX_SIZE 7 562 #define FIFO_ADD_OK 0 565 #define FIFO_EMPTY 2U 576 uint8_t * ptr_buffer ;
581 uint8_t num_records ;
624 uint8_t * ptrBuffer ,
808 #ifndef _SYSTEM_CONFIG_H 809 #define _SYSTEM_CONFIG_H 828 #define SYS_VERSION_STR "2.06" 829 #define SYS_VERSION 20600 833 #define SYS_CLK_FREQ 200000000ul 834 #define SYS_CLK_BUS_PERIPHERAL_1 100000000ul 835 #define SYS_CLK_BUS_PERIPHERAL_2 100000000ul 836 #define SYS_CLK_BUS_PERIPHERAL_3 100000000ul 837 #define SYS_CLK_BUS_PERIPHERAL_4 100000000ul 838 #define SYS_CLK_BUS_PERIPHERAL_5 100000000ul 839 #define SYS_CLK_BUS_PERIPHERAL_7 200000000ul 840 #define SYS_CLK_BUS_PERIPHERAL_8 100000000ul 841 #define SYS_CLK_CONFIG_PRIMARY_XTAL 0ul 842 #define SYS_CLK_CONFIG_SECONDARY_XTAL 32768ul 844 #define SYS_PORT_A_ANSEL 0x3F00 845 #define SYS_PORT_A_TRIS 0xFFED 846 #define SYS_PORT_A_LAT 0x0010 847 #define SYS_PORT_A_ODC 0x0000 848 #define SYS_PORT_A_CNPU 0x0020 849 #define SYS_PORT_A_CNPD 0x0000 850 #define SYS_PORT_A_CNEN 0x0021 851 #define SYS_PORT_B_ANSEL 0x10C8 852 #define SYS_PORT_B_TRIS 0x91FF 853 #define SYS_PORT_B_LAT 0x0000 854 #define SYS_PORT_B_ODC 0x0000 855 #define SYS_PORT_B_CNPU 0x0000 856 #define SYS_PORT_B_CNPD 0x0000 857 #define SYS_PORT_B_CNEN 0x0000 858 #define SYS_PORT_C_ANSEL 0xCFE1 859 #define SYS_PORT_C_TRIS 0xFFFF 860 #define SYS_PORT_C_LAT 0x0000 861 #define SYS_PORT_C_ODC 0x0000 862 #define SYS_PORT_C_CNPU 0x0000 863 #define SYS_PORT_C_CNPD 0x0000 864 #define SYS_PORT_C_CNEN 0x0000 865 #define SYS_PORT_D_ANSEL 0xC100 866 #define SYS_PORT_D_TRIS 0xFFFF 867 #define SYS_PORT_D_LAT 0x0000 868 #define SYS_PORT_D_ODC 0x0000 869 #define SYS_PORT_D_CNPU 0x0000 870 #define SYS_PORT_D_CNPD 0x0000 871 #define SYS_PORT_D_CNEN 0x0000 872 #define SYS_PORT_E_ANSEL 0xFC00 873 #define SYS_PORT_E_TRIS 0xFDFF 874 #define SYS_PORT_E_LAT 0x0000 875 #define SYS_PORT_E_ODC 0x0000 876 #define SYS_PORT_E_CNPU 0x0000 877 #define SYS_PORT_E_CNPD 0x0000 878 #define SYS_PORT_E_CNEN 0x0000 879 #define SYS_PORT_F_ANSEL 0xCEC0 880 #define SYS_PORT_F_TRIS 0xEFFF 881 #define SYS_PORT_F_LAT 0x0000 882 #define SYS_PORT_F_ODC 0x0000 883 #define SYS_PORT_F_CNPU 0x0000 884 #define SYS_PORT_F_CNPD 0x0000 885 #define SYS_PORT_F_CNEN 0x0000 886 #define SYS_PORT_G_ANSEL 0x8CBC 887 #define SYS_PORT_G_TRIS 0xDFFF 888 #define SYS_PORT_G_LAT 0x0000 889 #define SYS_PORT_G_ODC 0x0000 890 #define SYS_PORT_G_CNPU 0x0000 891 #define SYS_PORT_G_CNPD 0x0000 892 #define SYS_PORT_G_CNEN 0x0000 893 #define SYS_PORT_H_ANSEL 0x0070 894 #define SYS_PORT_H_TRIS 0xB3FB 895 #define SYS_PORT_H_LAT 0x0000 896 #define SYS_PORT_H_ODC 0x0000 897 #define SYS_PORT_H_CNPU 0x0000 898 #define SYS_PORT_H_CNPD 0x0000 899 #define SYS_PORT_H_CNEN 0x0000 900 #define SYS_PORT_J_ANSEL 0x0000 901 #define SYS_PORT_J_TRIS 0x8B7F 902 #define SYS_PORT_J_LAT 0x0080 903 #define SYS_PORT_J_ODC 0x0000 904 #define SYS_PORT_J_CNPU 0x0000 905 #define SYS_PORT_J_CNPD 0x0000 906 #define SYS_PORT_J_CNEN 0x0800 907 #define SYS_PORT_K_ANSEL 0xFF00 908 #define SYS_PORT_K_TRIS 0xFFFF 909 #define SYS_PORT_K_LAT 0x0000 910 #define SYS_PORT_K_ODC 0x0000 911 #define SYS_PORT_K_CNPU 0x0000 912 #define SYS_PORT_K_CNPD 0x0000 913 #define SYS_PORT_K_CNEN 0x0000 917 #define SYS_TMR_POWER_STATE SYS_MODULE_POWER_RUN_FULL 918 #define SYS_TMR_DRIVER_INDEX DRV_TMR_INDEX_0 919 #define SYS_TMR_MAX_CLIENT_OBJECTS 5 920 #define SYS_TMR_FREQUENCY 1000 921 #define SYS_TMR_FREQUENCY_TOLERANCE 10 922 #define SYS_TMR_UNIT_RESOLUTION 10000 923 #define SYS_TMR_CLIENT_TOLERANCE 10 924 #define SYS_TMR_INTERRUPT_NOTIFICATION false 930 #define DRV_IC_DRIVER_MODE_STATIC 933 #define DRV_SPI_NUMBER_OF_MODULES 6 936 #define DRV_SPI_POLLED 1 937 #define DRV_SPI_ISR 0 938 #define DRV_SPI_MASTER 1 939 #define DRV_SPI_SLAVE 0 941 #define DRV_SPI_EBM 1 942 #define DRV_SPI_8BIT 1 943 #define DRV_SPI_16BIT 1 944 #define DRV_SPI_32BIT 0 945 #define DRV_SPI_DMA 0 947 #define DRV_SPI_INSTANCES_NUMBER 3 948 #define DRV_SPI_CLIENTS_NUMBER 3 949 #define DRV_SPI_ELEMENTS_PER_QUEUE 10 951 #define DRV_SPI_SPI_ID_IDX0 SPI_ID_1 952 #define DRV_SPI_TASK_MODE_IDX0 DRV_SPI_TASK_MODE_POLLED 953 #define DRV_SPI_SPI_MODE_IDX0 DRV_SPI_MODE_MASTER 954 #define DRV_SPI_ALLOW_IDLE_RUN_IDX0 false 955 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX0 DRV_SPI_PROTOCOL_TYPE_FRAMED 956 #define DRV_SPI_FRAME_SYNC_PULSE_IDX0 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 957 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX0 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 958 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX0 SPI_FRAME_PULSE_DIRECTION_OUTPUT 959 #define DRV_SPI_FRAME_PULSE_EDGE_IDX0 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 960 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX0 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 961 #define DRV_SPI_COMM_WIDTH_IDX0 SPI_COMMUNICATION_WIDTH_16BITS 962 #define DRV_SPI_CLOCK_SOURCE_IDX0 SPI_BAUD_RATE_PBCLK_CLOCK 963 #define DRV_SPI_SPI_CLOCK_IDX0 CLK_BUS_PERIPHERAL_2 964 #define DRV_SPI_BAUD_RATE_IDX0 1000000 965 #define DRV_SPI_BUFFER_TYPE_IDX0 DRV_SPI_BUFFER_TYPE_ENHANCED 966 #define DRV_SPI_CLOCK_MODE_IDX0 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 967 #define DRV_SPI_INPUT_PHASE_IDX0 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 968 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX0 0xFFFF 969 #define DRV_SPI_QUEUE_SIZE_IDX0 10 970 #define DRV_SPI_RESERVED_JOB_IDX0 1 972 #define DRV_SPI_SPI_ID_IDX1 SPI_ID_2 973 #define DRV_SPI_TASK_MODE_IDX1 DRV_SPI_TASK_MODE_POLLED 974 #define DRV_SPI_SPI_MODE_IDX1 DRV_SPI_MODE_MASTER 975 #define DRV_SPI_ALLOW_IDLE_RUN_IDX1 false 976 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX1 DRV_SPI_PROTOCOL_TYPE_FRAMED 977 #define DRV_SPI_FRAME_SYNC_PULSE_IDX1 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 978 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX1 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 979 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX1 SPI_FRAME_PULSE_DIRECTION_OUTPUT 980 #define DRV_SPI_FRAME_PULSE_EDGE_IDX1 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 981 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX1 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 982 #define DRV_SPI_COMM_WIDTH_IDX1 SPI_COMMUNICATION_WIDTH_8BITS 983 #define DRV_SPI_CLOCK_SOURCE_IDX1 SPI_BAUD_RATE_PBCLK_CLOCK 984 #define DRV_SPI_SPI_CLOCK_IDX1 CLK_BUS_PERIPHERAL_2 985 #define DRV_SPI_BAUD_RATE_IDX1 1000000 986 #define DRV_SPI_BUFFER_TYPE_IDX1 DRV_SPI_BUFFER_TYPE_ENHANCED 987 #define DRV_SPI_CLOCK_MODE_IDX1 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 988 #define DRV_SPI_INPUT_PHASE_IDX1 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 989 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX1 0xFF 990 #define DRV_SPI_QUEUE_SIZE_IDX1 10 991 #define DRV_SPI_RESERVED_JOB_IDX1 1 993 #define DRV_SPI_SPI_ID_IDX2 SPI_ID_4 994 #define DRV_SPI_TASK_MODE_IDX2 DRV_SPI_TASK_MODE_POLLED 995 #define DRV_SPI_SPI_MODE_IDX2 DRV_SPI_MODE_MASTER 996 #define DRV_SPI_ALLOW_IDLE_RUN_IDX2 false 997 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX2 DRV_SPI_PROTOCOL_TYPE_FRAMED 998 #define DRV_SPI_FRAME_SYNC_PULSE_IDX2 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 999 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX2 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 1000 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX2 SPI_FRAME_PULSE_DIRECTION_OUTPUT 1001 #define DRV_SPI_FRAME_PULSE_EDGE_IDX2 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 1002 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX2 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 1003 #define DRV_SPI_COMM_WIDTH_IDX2 SPI_COMMUNICATION_WIDTH_16BITS 1004 #define DRV_SPI_CLOCK_SOURCE_IDX2 SPI_BAUD_RATE_PBCLK_CLOCK 1005 #define DRV_SPI_SPI_CLOCK_IDX2 CLK_BUS_PERIPHERAL_2 1006 #define DRV_SPI_BAUD_RATE_IDX2 500000 1007 #define DRV_SPI_BUFFER_TYPE_IDX2 DRV_SPI_BUFFER_TYPE_ENHANCED 1008 #define DRV_SPI_CLOCK_MODE_IDX2 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 1009 #define DRV_SPI_INPUT_PHASE_IDX2 SPI_INPUT_SAMPLING_PHASE_AT_END 1010 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX2 0x0000 1011 #define DRV_SPI_QUEUE_SIZE_IDX2 10 1012 #define DRV_SPI_RESERVED_JOB_IDX2 1 1014 #define DRV_TMR_INTERRUPT_MODE true 1016 #define DRV_TMR_PERIPHERAL_ID_IDX0 TMR_ID_2 1017 #define DRV_TMR_INTERRUPT_SOURCE_IDX0 INT_SOURCE_TIMER_2 1018 #define DRV_TMR_INTERRUPT_VECTOR_IDX0 INT_VECTOR_T2 1019 #define DRV_TMR_ISR_VECTOR_IDX0 _TIMER_2_VECTOR 1020 #define DRV_TMR_INTERRUPT_PRIORITY_IDX0 INT_PRIORITY_LEVEL4 1021 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0 1022 #define DRV_TMR_CLOCK_SOURCE_IDX0 DRV_TMR_CLKSOURCE_INTERNAL 1023 #define DRV_TMR_PRESCALE_IDX0 TMR_PRESCALE_VALUE_8 1024 #define DRV_TMR_OPERATION_MODE_IDX0 DRV_TMR_OPERATION_MODE_16_BIT 1025 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0 false 1026 #define DRV_TMR_POWER_STATE_IDX0 1027 #define DRV_TMR_PERIPHERAL_ID_IDX1 TMR_ID_7 1028 #define DRV_TMR_INTERRUPT_SOURCE_IDX1 INT_SOURCE_TIMER_7 1029 #define DRV_TMR_INTERRUPT_VECTOR_IDX1 INT_VECTOR_T7 1030 #define DRV_TMR_ISR_VECTOR_IDX1 _TIMER_7_VECTOR 1031 #define DRV_TMR_INTERRUPT_PRIORITY_IDX1 INT_PRIORITY_LEVEL3 1032 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX1 INT_SUBPRIORITY_LEVEL0 1033 #define DRV_TMR_CLOCK_SOURCE_IDX1 DRV_TMR_CLKSOURCE_INTERNAL 1034 #define DRV_TMR_PRESCALE_IDX1 TMR_PRESCALE_VALUE_16 1035 #define DRV_TMR_OPERATION_MODE_IDX1 DRV_TMR_OPERATION_MODE_16_BIT 1036 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX1 false 1037 #define DRV_TMR_POWER_STATE_IDX1 1039 #define DRV_TMR_PERIPHERAL_ID_IDX2 TMR_ID_6 1040 #define DRV_TMR_INTERRUPT_SOURCE_IDX2 INT_SOURCE_TIMER_6 1041 #define DRV_TMR_INTERRUPT_VECTOR_IDX2 INT_VECTOR_T6 1042 #define DRV_TMR_ISR_VECTOR_IDX2 _TIMER_6_VECTOR 1043 #define DRV_TMR_INTERRUPT_PRIORITY_IDX2 INT_PRIORITY_LEVEL1 1044 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX2 INT_SUBPRIORITY_LEVEL0 1045 #define DRV_TMR_CLOCK_SOURCE_IDX2 DRV_TMR_CLKSOURCE_INTERNAL 1046 #define DRV_TMR_PRESCALE_IDX2 TMR_PRESCALE_VALUE_16 1047 #define DRV_TMR_OPERATION_MODE_IDX2 DRV_TMR_OPERATION_MODE_16_BIT 1048 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX2 false 1049 #define DRV_TMR_POWER_STATE_IDX2 1051 #define DRV_TMR_PERIPHERAL_ID_IDX3 TMR_ID_1 1052 #define DRV_TMR_INTERRUPT_SOURCE_IDX3 INT_SOURCE_TIMER_1 1053 #define DRV_TMR_INTERRUPT_VECTOR_IDX3 INT_VECTOR_T1 1054 #define DRV_TMR_ISR_VECTOR_IDX3 _TIMER_1_VECTOR 1055 #define DRV_TMR_INTERRUPT_PRIORITY_IDX3 INT_PRIORITY_LEVEL2 1056 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX3 INT_SUBPRIORITY_LEVEL0 1057 #define DRV_TMR_CLOCK_SOURCE_IDX3 DRV_TMR_CLKSOURCE_INTERNAL 1058 #define DRV_TMR_PRESCALE_IDX3 TMR_PRESCALE_VALUE_256 1059 #define DRV_TMR_OPERATION_MODE_IDX3 DRV_TMR_OPERATION_MODE_16_BIT 1060 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX3 false 1061 #define DRV_TMR_POWER_STATE_IDX3 1063 #define DRV_TMR_PERIPHERAL_ID_IDX4 TMR_ID_3 1064 #define DRV_TMR_INTERRUPT_SOURCE_IDX4 INT_SOURCE_TIMER_3 1065 #define DRV_TMR_INTERRUPT_VECTOR_IDX4 INT_VECTOR_T3 1066 #define DRV_TMR_ISR_VECTOR_IDX4 _TIMER_3_VECTOR 1067 #define DRV_TMR_INTERRUPT_PRIORITY_IDX4 INT_PRIORITY_LEVEL1 1068 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX4 INT_SUBPRIORITY_LEVEL0 1069 #define DRV_TMR_CLOCK_SOURCE_IDX4 DRV_TMR_CLKSOURCE_INTERNAL 1070 #define DRV_TMR_PRESCALE_IDX4 TMR_PRESCALE_VALUE_16 1071 #define DRV_TMR_OPERATION_MODE_IDX4 DRV_TMR_OPERATION_MODE_16_BIT 1072 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX4 false 1073 #define DRV_TMR_POWER_STATE_IDX4 1077 #define DRV_USART_INSTANCES_NUMBER 1 1078 #define DRV_USART_CLIENTS_NUMBER 1 1079 #define DRV_USART_INTERRUPT_MODE false 1080 #define DRV_USART_BYTE_MODEL_SUPPORT true 1081 #define DRV_USART_READ_WRITE_MODEL_SUPPORT false 1082 #define DRV_USART_BUFFER_QUEUE_SUPPORT false 1090 #define DRV_USBHS_DEVICE_SUPPORT true 1092 #define DRV_USBHS_HOST_SUPPORT false 1094 #define DRV_USBHS_INSTANCES_NUMBER 1 1096 #define DRV_USBHS_INTERRUPT_MODE true 1098 #define DRV_USBHS_ENDPOINTS_NUMBER 2 1101 #define USB_DEVICE_DRIVER_INITIALIZE_EXPLICIT 1103 #define USB_DEVICE_INSTANCES_NUMBER 1 1105 #define USB_DEVICE_EP0_BUFFER_SIZE 64 1107 #define USB_DEVICE_ENDPOINT_QUEUE_DEPTH_COMBINED 2 1115 #define LED1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 1116 #define LED1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 1117 #define LED1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 1118 #define LED1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 1119 #define LED1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 , Value ) 1121 #define LED2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 1122 #define LED2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 1123 #define LED2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 1124 #define LED2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 1125 #define LED2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 , Value ) 1127 #define DMP_FIRE_LEDToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 1128 #define DMP_FIRE_LEDOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 1129 #define DMP_FIRE_LEDOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 1130 #define DMP_FIRE_LEDStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 1131 #define DMP_FIRE_LEDStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 , Value ) 1133 #define HVPS_ENBToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 1134 #define HVPS_ENBOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 1135 #define HVPS_ENBOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 1136 #define HVPS_ENBStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 1137 #define HVPS_ENBStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 , Value ) 1139 #define RLY_HVPS_OUTToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 1140 #define RLY_HVPS_OUTOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 1141 #define RLY_HVPS_OUTOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 1142 #define RLY_HVPS_OUTStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 1143 #define RLY_HVPS_OUTStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 , Value ) 1145 #define RLY_WL_SPS_POLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 1146 #define RLY_WL_SPS_POLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 1147 #define RLY_WL_SPS_POLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 1148 #define RLY_WL_SPS_POLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 1149 #define RLY_WL_SPS_POLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 , Value ) 1151 #define RLY_LOGToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 1152 #define RLY_LOGOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 1153 #define RLY_LOGOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 1154 #define RLY_LOGStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 1155 #define RLY_LOGStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 , Value ) 1157 #define RLY_DMP_FIREToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 1158 #define RLY_DMP_FIREOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 1159 #define RLY_DMP_FIREOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 1160 #define RLY_DMP_FIREStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 1161 #define RLY_DMP_FIREStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 , Value ) 1163 #define RLY_AUXToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 1164 #define RLY_AUXOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 1165 #define RLY_AUXOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 1166 #define RLY_AUXStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 1167 #define RLY_AUXStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 , Value ) 1169 #define RLY_CCLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 1170 #define RLY_CCLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 1171 #define RLY_CCLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 1172 #define RLY_CCLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 1173 #define RLY_CCLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 , Value ) 1175 #define RLY_WL_MONToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 1176 #define RLY_WL_MONOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 1177 #define RLY_WL_MONOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 1178 #define RLY_WL_MONStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 1179 #define RLY_WL_MONStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 , Value ) 1181 #define RLY_ARMCFToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 1182 #define RLY_ARMCFOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 1183 #define RLY_ARMCFOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 1184 #define RLY_ARMCFStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 1185 #define RLY_ARMCFStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 , Value ) 1187 #define RLY_ARMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 1188 #define RLY_ARMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 1189 #define RLY_ARMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 1190 #define RLY_ARMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 1191 #define RLY_ARMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 , Value ) 1193 #define TPAN1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 1194 #define TPAN1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 1195 #define TPAN1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 1196 #define TPAN1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 1197 #define TPAN1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 , Value ) 1199 #define TPAN2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 1200 #define TPAN2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 1201 #define TPAN2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 1202 #define TPAN2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 1203 #define TPAN2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 , Value ) 1205 #define FSK_DAC_CSToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 1206 #define FSK_DAC_CSOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 1207 #define FSK_DAC_CSOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 1208 #define FSK_DAC_CSStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 1209 #define FSK_DAC_CSStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 , Value ) 1211 #define RLY_COMMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 1212 #define RLY_COMMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 1213 #define RLY_COMMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 1214 #define RLY_COMMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 1215 #define RLY_COMMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 , Value ) 1217 #define FSK_DAC_CLRToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 1218 #define FSK_DAC_CLROn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 1219 #define FSK_DAC_CLROff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 1220 #define FSK_DAC_CLRStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 1221 #define FSK_DAC_CLRStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 , Value ) 1223 #define WL_CPS_SWToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 1224 #define WL_CPS_SWOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 1225 #define WL_CPS_SWOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 1226 #define WL_CPS_SWStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 1227 #define WL_CPS_SWStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 , Value ) 1229 #define HVPS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_5 ) 1231 #define MAN_SIGStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_0 ) 1233 #define DMP_FIRE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_8 ) 1235 #define NEG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_4 ) 1237 #define POS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_15 ) 1239 #define DRUM1_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_2 ) 1241 #define SAFE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_1 ) 1243 #define DRUM2_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_0 ) 1245 #define LOG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_3 ) 1247 #define AUX_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_8 ) 1249 #define ARMCF_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_1 ) 1251 #define ARM_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_2 ) 1253 #define ARMCF_AUTO_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_13 ) 1255 #define FIRE_SW_OFFStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_8 ) 1257 #define FIRE_SW_ONStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_8 ) 1259 #define WL_SPS_POS_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_12 ) 1261 #define WL_SPS_NEG_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_13 ) 1262 #define MAN_CN_PORT_CHANNEL PORT_CHANNEL_A 1263 #define MAN_CN_PORT_BIT PORTS_BIT_POS_0 1264 #define MAN_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_A 1265 #define HVPS_CN_PORT_CHANNEL PORT_CHANNEL_J 1266 #define HVPS_CN_PORT_BIT PORTS_BIT_POS_11 1267 #define HVPS_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_J 1310 #ifndef _SYS_DEFINITIONS_H 1311 #define _SYS_DEFINITIONS_H 1319 #include <stdbool.h> 1320 #include "system/common/sys_common.h" 1321 #include "system/common/sys_module.h" 1366 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1405 #ifndef _DRV_COMMON_H 1406 #define _DRV_COMMON_H 1508 #define DRV_IO_ISBLOCKING( intent ) ( intent & DRV_IO_INTENT_BLOCKING ) 1518 #define DRV_IO_ISNONBLOCKING( intent ) ( intent & DRV_IO_INTENT_NONBLOCKING ) 1528 #define DRV_IO_ISEXCLUSIVE( intent ) ( intent & DRV_IO_INTENT_EXCLUSIVE ) 1584 #define DRV_HANDLE_INVALID ( ( ( DRV_HANDLE ) - 1 ) ) 1595 #define DRV_CONFIG_NOT_SUPPORTED ( ( ( unsigned short ) - 1 ) ) 1610 #define _PLIB_UNSUPPORTED 1618 #include "system/common/sys_module.h" 1630 #define DRV_IC_INDEX_0 0 1631 #define DRV_IC_INDEX_1 1 1632 #define DRV_IC_INDEX_2 2 1633 #define DRV_IC_INDEX_3 3 1634 #define DRV_IC_INDEX_4 4 1635 #define DRV_IC_INDEX_5 5 1636 #define DRV_IC_INDEX_6 6 1637 #define DRV_IC_INDEX_7 7 1638 #define DRV_IC_INDEX_8 8 1639 #define DRV_IC_INDEX_9 9 1640 #define DRV_IC_INDEX_10 10 1641 #define DRV_IC_INDEX_11 11 1642 #define DRV_IC_INDEX_12 12 1643 #define DRV_IC_INDEX_13 13 1644 #define DRV_IC_INDEX_14 14 1645 #define DRV_IC_INDEX_15 15 1677 const SYS_MODULE_INDEX index ,
1678 const SYS_MODULE_INIT *
const init ) ;
1700 const SYS_MODULE_INDEX drvIndex ,
1745 const SYS_MODULE_INDEX drvIndex ,
1878 #ifndef _DRV_IC_STATIC_H 1879 #define _DRV_IC_STATIC_H 1880 #define DRV_IC_Open( drvIndex , intent ) ( drvIndex ) 1881 #define DRV_IC_Close( handle ) 1920 #include "system/devcon/sys_devcon.h" 1921 #include "system/clk/sys_clk.h" 1922 #include "system/int/sys_int.h" 1923 #include "system/tmr/sys_tmr.h" 1965 #ifndef _DRV_ADC_STATIC_H 1966 #define _DRV_ADC_STATIC_H 1967 #include <stdbool.h> 1968 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1969 #include "peripheral/adchs/plib_adchs.h" 1970 #include "peripheral/int/plib_int.h" 2010 uint8_t bufIndex ) ;
2014 uint8_t bufIndex ) ;
2064 #ifndef _DRV_TMR_STATIC_H 2065 #define _DRV_TMR_STATIC_H 2114 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 2115 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 2116 #include "peripheral/tmr/plib_tmr.h" 2152 #ifndef _TMR_DEFINITIONS_PIC32M_H 2153 #define _TMR_DEFINITIONS_PIC32M_H 2211 #include "system/int/sys_int.h" 2212 #include "system/clk/sys_clk.h" 2231 #define DRV_TMR_INDEX_0 0 2232 #define DRV_TMR_INDEX_1 1 2233 #define DRV_TMR_INDEX_2 2 2234 #define DRV_TMR_INDEX_3 3 2235 #define DRV_TMR_INDEX_4 4 2236 #define DRV_TMR_INDEX_5 5 2237 #define DRV_TMR_INDEX_6 6 2238 #define DRV_TMR_INDEX_7 7 2239 #define DRV_TMR_INDEX_8 8 2240 #define DRV_TMR_INDEX_9 9 2241 #define DRV_TMR_INDEX_10 10 2242 #define DRV_TMR_INDEX_11 11 2253 #define DRV_TMR_INDEX_COUNT TMR_NUMBER_OF_MODULES 2338 uint32_t dividerMin ;
2340 uint32_t dividerMax ;
2343 uint32_t dividerStep ;
2359 SYS_MODULE_INIT moduleInit ;
2361 TMR_MODULE_ID tmrId ;
2365 TMR_PRESCALE prescale ;
2369 INT_SOURCE interruptSource ;
2377 bool asyncWriteEnable ;
2392 uint32_t alarmCount ) ;
2454 const SYS_MODULE_INDEX drvIndex ,
2455 const SYS_MODULE_INIT *
const init ) ;
2495 SYS_MODULE_OBJ
object ) ;
2542 SYS_MODULE_OBJ
object ) ;
2576 SYS_MODULE_OBJ
object ) ;
2630 const SYS_MODULE_INDEX index ,
2731 uint32_t counterPeriod ) ;
3221 TMR_PRESCALE preScale ) ;
3461 #ifndef _DRV_TMR_DEPRECATED_H 3462 #define _DRV_TMR_DEPRECATED_H 3503 #define DRV_TMR_Tasks_ISR( object ) DRV_TMR_Tasks ( object ) 3567 #define DRV_TMR_CounterValue16BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3632 #define DRV_TMR_CounterValue32BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3691 #define DRV_TMR_CounterValue16BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3752 #define DRV_TMR_CounterValue32BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3811 #define DRV_TMR_Alarm16BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3872 #define DRV_TMR_Alarm32BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3902 #define DRV_TMR_AlarmPeriod16BitSet( handle , value ) DRV_TMR_AlarmPeriodSet ( handle , value ) 3934 #define DRV_TMR_AlarmPeriod32BitSet( handle , period ) DRV_TMR_AlarmPeriodSet ( handle , period ) 3965 #define DRV_TMR_AlarmPeriod16BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3997 #define DRV_TMR_AlarmPeriod32BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 4059 #define DRV_TMR_Alarm16BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 4124 #define DRV_TMR_Alarm32BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 4141 #include "peripheral/tmr/plib_tmr.h" 4142 #include "peripheral/int/plib_int.h" 4144 #define DRV_TIMER_DIVIDER_MAX_32BIT 0xffffffff 4146 #define DRV_TIMER_DIVIDER_MIN_32BIT 0x2 4148 #define DRV_TIMER_DIVIDER_MAX_16BIT 0x10000 4150 #define DRV_TIMER_DIVIDER_MIN_16BIT 0x2 4169 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 0)));
4175 static inline SYS_STATUS
4178 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 2)));
4189 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 4)));
4200 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 6)));
4210 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 8)));
4219 TMR_PRESCALE prescale ) ;
4250 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 10)));
4279 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 12)));
4285 static inline SYS_STATUS
4288 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 14)));
4299 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 16)));
4310 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 18)));
4320 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 20)));
4329 TMR_PRESCALE prescale ) ;
4360 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 22)));
4389 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 24)));
4395 static inline SYS_STATUS
4398 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 26)));
4409 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 28)));
4420 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 30)));
4430 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 0)));
4439 TMR_PRESCALE prescale ) ;
4470 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 2)));
4499 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 4)));
4505 static inline SYS_STATUS
4508 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 6)));
4519 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 8)));
4530 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 10)));
4540 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 12)));
4549 TMR_PRESCALE prescale ) ;
4580 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 14)));
4609 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 16)));
4615 static inline SYS_STATUS
4618 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 18)));
4629 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 20)));
4640 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 22)));
4650 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 24)));
4659 TMR_PRESCALE prescale ) ;
4690 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 26)));
4709 #include "peripheral/int/plib_int.h" 4751 #ifndef _DRV_PMP_STATIC_H 4752 #define _DRV_PMP_STATIC_H 4753 #include "peripheral/pmp/plib_pmp.h" 4768 PMP_DATA_WAIT_STATES dataWait ,
4769 PMP_STROBE_WAIT_STATES strobeWait ,
4770 PMP_DATA_HOLD_STATES dataHold ) ;
4825 #ifndef _DRV_USART_STATIC_H 4826 #define _DRV_USART_STATIC_H 4865 #ifndef _DRV_USART_STATIC_LOCAL_H 4866 #define _DRV_USART_STATIC_LOCAL_H 4873 #include <stdbool.h> 4910 #ifndef _DRV_USART_H 4911 #define _DRV_USART_H 4951 #ifndef _DRV_USART_DEFINITIONS_H 4952 #define _DRV_USART_DEFINITIONS_H 4958 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 4959 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 4996 #ifndef _PLIB_USART_H 4997 #define _PLIB_USART_H 5040 #ifndef _USART_PROCESSOR_H 5041 #define _USART_PROCESSOR_H 5050 #include <stdbool.h> 5051 #error "No Processor Family specified" 5095 USART_MODULE_ID index ) ;
5125 USART_MODULE_ID index ) ;
5157 USART_MODULE_ID index ) ;
5191 USART_MODULE_ID index ,
5192 USART_BRG_CLOCK_SOURCE brgClockSource ) ;
5221 USART_BRG_CLOCK_SOURCE
5223 USART_MODULE_ID index ) ;
5277 USART_MODULE_ID index ) ;
5307 USART_MODULE_ID index ) ;
5336 USART_MODULE_ID index ) ;
5368 USART_MODULE_ID index ) ;
5399 USART_MODULE_ID index ) ;
5441 USART_MODULE_ID index ) ;
5474 USART_MODULE_ID index ) ;
5506 USART_MODULE_ID index ) ;
5547 USART_MODULE_ID index ,
5548 uint32_t clockFrequency ,
5549 uint32_t baudRate ) ;
5590 USART_MODULE_ID index ,
5591 uint32_t clockFrequency ,
5592 uint32_t baudRate ) ;
5625 USART_MODULE_ID index ,
5626 int32_t clockFrequency ) ;
5661 USART_MODULE_ID index ,
5696 USART_MODULE_ID index ) ;
5731 USART_MODULE_ID index ,
5766 USART_MODULE_ID index ) ;
5798 USART_MODULE_ID index ) ;
5832 USART_MODULE_ID index ) ;
5865 USART_MODULE_ID index ) ;
5898 USART_MODULE_ID index ) ;
5932 USART_MODULE_ID index ,
5977 USART_MODULE_ID index ) ;
6011 USART_MODULE_ID index ) ;
6047 USART_MODULE_ID index ) ;
6084 USART_MODULE_ID index ,
6124 USART_MODULE_ID index ) ;
6162 USART_MODULE_ID index ) ;
6197 USART_MODULE_ID index ) ;
6231 USART_MODULE_ID index ) ;
6265 USART_MODULE_ID index ) ;
6298 USART_MODULE_ID index ) ;
6330 USART_MODULE_ID index ) ;
6362 USART_MODULE_ID index ) ;
6395 USART_MODULE_ID index ) ;
6429 USART_MODULE_ID index ) ;
6458 USART_MODULE_ID index ) ;
6487 USART_MODULE_ID index ) ;
6519 USART_MODULE_ID index ) ;
6551 USART_MODULE_ID index ) ;
6581 USART_MODULE_ID index ) ;
6611 USART_MODULE_ID index ) ;
6640 USART_MODULE_ID index ) ;
6669 USART_MODULE_ID index ) ;
6703 USART_MODULE_ID index ,
6704 USART_TRANSMIT_INTR_MODE fifolevel ) ;
6736 USART_MODULE_ID index ,
6737 USART_RECEIVE_INTR_MODE interruptMode ) ;
6770 USART_MODULE_ID index ,
6771 USART_LINECONTROL_MODE dataFlowConfig ) ;
6804 USART_MODULE_ID index ,
6805 USART_HANDSHAKE_MODE handshakeConfig ) ;
6838 USART_MODULE_ID index ,
6869 USART_MODULE_ID index ) ;
6898 USART_MODULE_ID index ) ;
6929 USART_MODULE_ID index ) ;
6960 USART_MODULE_ID index ) ;
6990 USART_MODULE_ID index ) ;
7022 USART_MODULE_ID index ,
7023 USART_OPERATION_MODE operationmode ) ;
7053 USART_MODULE_ID index ) ;
7086 USART_MODULE_ID index ) ;
7115 USART_MODULE_ID index ) ;
7145 USART_MODULE_ID index ) ;
7181 USART_MODULE_ID index ) ;
7232 USART_MODULE_ID index ,
7235 bool wakeFromSleep ,
7280 USART_MODULE_ID index ,
7281 USART_RECEIVE_INTR_MODE receiveInterruptMode ,
7282 USART_TRANSMIT_INTR_MODE transmitInterruptMode ,
7283 USART_OPERATION_MODE operationMode ) ;
7329 USART_MODULE_ID index ,
7330 uint32_t systemClock ,
7376 USART_MODULE_ID index ) ;
7397 USART_MODULE_ID index ) ;
7418 USART_MODULE_ID index ) ;
7452 USART_MODULE_ID index ) ;
7479 USART_MODULE_ID index ) ;
7505 USART_MODULE_ID index ) ;
7532 USART_MODULE_ID index ) ;
7558 USART_MODULE_ID index ) ;
7583 USART_MODULE_ID index ) ;
7609 USART_MODULE_ID index ) ;
7634 USART_MODULE_ID index ) ;
7660 USART_MODULE_ID index ) ;
7685 USART_MODULE_ID index ) ;
7711 USART_MODULE_ID index ) ;
7738 USART_MODULE_ID index ) ;
7764 USART_MODULE_ID index ) ;
7790 USART_MODULE_ID index ) ;
7817 USART_MODULE_ID index ) ;
7844 USART_MODULE_ID index ) ;
7871 USART_MODULE_ID index ) ;
7897 USART_MODULE_ID index ) ;
7922 USART_MODULE_ID index ) ;
7948 USART_MODULE_ID index ) ;
7975 USART_MODULE_ID index ) ;
8001 USART_MODULE_ID index ) ;
8027 USART_MODULE_ID index ) ;
8052 USART_MODULE_ID index ) ;
8077 USART_MODULE_ID index ) ;
8102 USART_MODULE_ID index ) ;
8128 USART_MODULE_ID index ) ;
8153 USART_MODULE_ID index ) ;
8179 USART_MODULE_ID index ) ;
8205 USART_MODULE_ID index ) ;
8230 USART_MODULE_ID index ) ;
8256 USART_MODULE_ID index ) ;
8281 USART_MODULE_ID index ) ;
8306 USART_MODULE_ID index ) ;
8333 USART_MODULE_ID index ) ;
8358 USART_MODULE_ID index ) ;
8384 USART_MODULE_ID index ) ;
8449 #include "system/common/sys_common.h" 8450 #include "system/common/sys_module.h" 8462 #include "system/int/sys_int.h" 8534 #ifndef _SYS_DMA_DEFINITIONS_H 8535 #define _SYS_DMA_DEFINITIONS_H 8541 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 8542 #include "system/common/sys_common.h" 8543 #include "system/common/sys_module.h" 8613 #ifndef _PLIB_DMA_PROCESSOR_H 8614 #define _PLIB_DMA_PROCESSOR_H 8615 #error "Can't find header" 8659 DMA_MODULE_ID index ,
8660 DMA_CHANNEL channel ) ;
8694 DMA_MODULE_ID index ,
8695 DMA_CHANNEL channel ,
8696 DMA_CHANNEL_COLLISION collisonType ) ;
8728 DMA_MODULE_ID index ,
8729 DMA_CHANNEL channel ) ;
8761 DMA_MODULE_ID index ,
8762 DMA_CHANNEL channel ) ;
8800 DMA_MODULE_ID index ,
8801 DMA_CHANNEL channel ,
8802 DMA_CHANNEL_PRIORITY channelPriority ) ;
8831 DMA_CHANNEL_PRIORITY
8833 DMA_MODULE_ID index ,
8834 DMA_CHANNEL channel ) ;
8862 DMA_MODULE_ID index ,
8863 DMA_CHANNEL_PRIORITY channelPriority ) ;
8888 DMA_CHANNEL_PRIORITY
8890 DMA_MODULE_ID index ) ;
8920 DMA_MODULE_ID index ,
8921 DMA_CHANNEL channel ) ;
8952 DMA_MODULE_ID index ,
8953 DMA_CHANNEL channel ) ;
8982 DMA_MODULE_ID index ,
8983 DMA_CHANNEL channel ) ;
9012 DMA_MODULE_ID index ,
9013 DMA_CHANNEL channel ) ;
9044 DMA_MODULE_ID index ,
9045 DMA_CHANNEL channel ) ;
9074 DMA_MODULE_ID index ,
9075 DMA_CHANNEL channel ) ;
9106 DMA_MODULE_ID index ,
9107 DMA_CHANNEL channel ) ;
9138 DMA_MODULE_ID index ,
9139 DMA_CHANNEL channel ) ;
9168 DMA_MODULE_ID index ,
9169 DMA_CHANNEL channel ) ;
9200 DMA_MODULE_ID index ,
9201 DMA_CHANNEL channel ) ;
9230 DMA_MODULE_ID index ,
9231 DMA_CHANNEL channel ) ;
9261 DMA_MODULE_ID index ,
9262 DMA_CHANNEL channel ) ;
9292 DMA_MODULE_ID index ,
9293 DMA_CHANNEL channel ) ;
9323 DMA_MODULE_ID index ,
9324 DMA_CHANNEL channel ) ;
9354 DMA_MODULE_ID index ,
9355 DMA_CHANNEL channel ) ;
9386 DMA_MODULE_ID index ,
9387 DMA_CHANNEL channel ) ;
9418 DMA_MODULE_ID index ,
9419 DMA_CHANNEL channel ,
9420 DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection ) ;
9449 DMA_CHANNEL_TRANSFER_DIRECTION
9451 DMA_MODULE_ID index ,
9452 DMA_CHANNEL channel ) ;
9488 DMA_MODULE_ID index ,
9489 DMA_CHANNEL channel ,
9491 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9524 DMA_MODULE_ID index ,
9525 DMA_CHANNEL channel ,
9526 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9557 DMA_MODULE_ID index ,
9558 DMA_CHANNEL channel ,
9559 uint16_t peripheraladdress ) ;
9587 DMA_MODULE_ID index ,
9588 DMA_CHANNEL channel ) ;
9619 DMA_MODULE_ID index ,
9620 DMA_CHANNEL channel ,
9621 uint16_t transferCount ) ;
9649 DMA_MODULE_ID index ,
9650 DMA_CHANNEL channel ) ;
9683 DMA_MODULE_ID index ,
9684 DMA_CHANNEL channel ,
9685 DMA_SOURCE_ADDRESSING_MODE sourceAddressMode ) ;
9713 DMA_SOURCE_ADDRESSING_MODE
9715 DMA_MODULE_ID index ,
9716 DMA_CHANNEL channel ) ;
9749 DMA_MODULE_ID index ,
9750 DMA_CHANNEL channel ,
9751 DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode ) ;
9780 DMA_DESTINATION_ADDRESSING_MODE
9782 DMA_MODULE_ID index ,
9783 DMA_CHANNEL channel ) ;
9816 DMA_MODULE_ID index ,
9817 DMA_CHANNEL channel ,
9818 DMA_CHANNEL_ADDRESSING_MODE channelAddressMode ) ;
9846 DMA_CHANNEL_ADDRESSING_MODE
9848 DMA_MODULE_ID index ,
9849 DMA_CHANNEL channel ) ;
9887 DMA_MODULE_ID index ,
9888 DMA_CHANNEL channel ,
9889 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9925 DMA_MODULE_ID index ,
9926 DMA_CHANNEL channel ,
9927 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9962 DMA_MODULE_ID index ,
9963 DMA_CHANNEL channel ,
9964 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9993 DMA_CHANNEL_INT_SOURCE
9995 DMA_MODULE_ID index ,
9996 DMA_CHANNEL channel ) ;
10031 DMA_MODULE_ID index ,
10032 DMA_CHANNEL channel ,
10033 DMA_TRIGGER_SOURCE IRQnum ) ;
10068 DMA_MODULE_ID index ,
10069 DMA_CHANNEL channel ,
10070 DMA_TRIGGER_SOURCE IRQ ) ;
10101 DMA_MODULE_ID index ,
10102 DMA_CHANNEL channel ,
10103 DMA_CHANNEL_DATA_SIZE channelDataSize ) ;
10130 DMA_CHANNEL_DATA_SIZE
10132 DMA_MODULE_ID index ,
10133 DMA_CHANNEL channel ) ;
10167 DMA_MODULE_ID index ,
10168 DMA_CHANNEL channel ,
10169 DMA_TRANSFER_MODE channeltransferMode ) ;
10201 DMA_MODULE_ID index ,
10202 DMA_CHANNEL channel ) ;
10231 DMA_MODULE_ID index ,
10232 DMA_CHANNEL channel ) ;
10262 DMA_MODULE_ID index ,
10263 DMA_CHANNEL channel ) ;
10292 DMA_MODULE_ID index ,
10293 DMA_CHANNEL channel ) ;
10321 DMA_MODULE_ID index ,
10322 DMA_CHANNEL channel ) ;
10352 DMA_MODULE_ID index ,
10353 DMA_CHANNEL channel ) ;
10380 DMA_MODULE_ID index ,
10381 DMA_CHANNEL channel ) ;
10417 DMA_MODULE_ID index ,
10418 DMA_CHANNEL channel ) ;
10449 DMA_MODULE_ID index ,
10450 DMA_CHANNEL channel ) ;
10483 DMA_MODULE_ID index ) ;
10512 DMA_MODULE_ID index ) ;
10542 DMA_MODULE_ID index ) ;
10571 DMA_MODULE_ID index ) ;
10600 DMA_MODULE_ID index ) ;
10630 DMA_MODULE_ID index ) ;
10658 DMA_MODULE_ID index ) ;
10686 DMA_MODULE_ID index ) ;
10714 DMA_MODULE_ID index ) ;
10743 DMA_MODULE_ID index ) ;
10771 DMA_MODULE_ID index ) ;
10805 DMA_MODULE_ID index ) ;
10835 DMA_MODULE_ID index ) ;
10865 DMA_MODULE_ID index ) ;
10894 DMA_MODULE_ID index ) ;
10929 DMA_MODULE_ID index ,
10930 DMA_CHANNEL channel ) ;
10959 DMA_MODULE_ID index ) ;
10991 DMA_MODULE_ID index ,
10992 DMA_CRC_TYPE CRCType ) ;
11023 DMA_MODULE_ID index ) ;
11053 DMA_MODULE_ID index ) ;
11083 DMA_MODULE_ID index ) ;
11113 DMA_MODULE_ID index ) ;
11142 DMA_MODULE_ID index ) ;
11172 DMA_MODULE_ID index ) ;
11201 DMA_MODULE_ID index ) ;
11231 DMA_MODULE_ID index ,
11232 uint8_t polyLength ) ;
11261 DMA_MODULE_ID index ) ;
11290 DMA_MODULE_ID index ,
11291 DMA_CRC_BIT_ORDER bitOrder ) ;
11322 DMA_MODULE_ID index ) ;
11351 DMA_MODULE_ID index ) ;
11381 DMA_MODULE_ID index ,
11382 DMA_CRC_BYTE_ORDER byteOrder ) ;
11411 DMA_MODULE_ID index ) ;
11442 DMA_MODULE_ID index ) ;
11474 DMA_MODULE_ID index ,
11475 uint32_t DMACRCdata ) ;
11506 DMA_MODULE_ID index ) ;
11539 DMA_MODULE_ID index ,
11540 uint32_t DMACRCXOREnableMask ) ;
11578 DMA_MODULE_ID index ,
11579 DMA_CHANNEL dmaChannel ) ;
11616 DMA_MODULE_ID index ,
11617 DMA_CHANNEL dmaChannel ,
11618 uint32_t sourceStartAddress ) ;
11652 DMA_MODULE_ID index ,
11653 DMA_CHANNEL dmaChannel ) ;
11691 DMA_MODULE_ID index ,
11692 DMA_CHANNEL dmaChannel ,
11693 uint32_t destinationStartAddress ) ;
11733 DMA_MODULE_ID index ,
11734 DMA_CHANNEL dmaChannel ) ;
11773 DMA_MODULE_ID index ,
11774 DMA_CHANNEL dmaChannel ,
11775 uint16_t sourceSize ) ;
11810 DMA_MODULE_ID index ,
11811 DMA_CHANNEL dmaChannel ) ;
11848 DMA_MODULE_ID index ,
11849 DMA_CHANNEL dmaChannel ,
11850 uint16_t destinationSize ) ;
11884 DMA_MODULE_ID index ,
11885 DMA_CHANNEL dmaChannel ) ;
11920 DMA_MODULE_ID index ,
11921 DMA_CHANNEL dmaChannel ) ;
11956 DMA_MODULE_ID index ,
11957 DMA_CHANNEL dmaChannel ) ;
11994 DMA_MODULE_ID index ,
11995 DMA_CHANNEL dmaChannel ,
11996 uint16_t CellSize ) ;
12030 DMA_MODULE_ID index ,
12031 DMA_CHANNEL dmaChannel ) ;
12068 DMA_MODULE_ID index ,
12069 DMA_CHANNEL dmaChannel ) ;
12108 DMA_MODULE_ID index ,
12109 DMA_CHANNEL dmaChannel ,
12110 uint16_t patternData ) ;
12154 DMA_MODULE_ID index ,
12155 DMA_CHANNEL dmaChannel ,
12156 DMA_INT_TYPE dmaINTSource ) ;
12191 DMA_MODULE_ID index ,
12192 DMA_CHANNEL dmaChannel ,
12193 DMA_INT_TYPE dmaINTSource ) ;
12229 DMA_MODULE_ID index ,
12230 DMA_CHANNEL dmaChannel ,
12231 DMA_INT_TYPE dmaINTSource ) ;
12265 DMA_MODULE_ID index ,
12266 DMA_CHANNEL dmaChannel ,
12267 DMA_INT_TYPE dmaINTSource ) ;
12301 DMA_MODULE_ID index ,
12302 DMA_CHANNEL dmaChannel ,
12303 DMA_INT_TYPE dmaINTSource ) ;
12341 DMA_MODULE_ID index ,
12342 DMA_CHANNEL dmaChannel ,
12343 DMA_INT_TYPE dmaINTSource ) ;
12376 DMA_MODULE_ID index ,
12377 DMA_CHANNEL dmaChannel ,
12378 DMA_PATTERN_LENGTH patternLen ) ;
12411 DMA_MODULE_ID index ,
12412 DMA_CHANNEL dmaChannel ) ;
12442 DMA_MODULE_ID index ,
12443 DMA_CHANNEL channel ) ;
12476 DMA_MODULE_ID index ,
12477 DMA_CHANNEL channel ) ;
12507 DMA_MODULE_ID index ,
12508 DMA_CHANNEL channel ) ;
12540 DMA_MODULE_ID index ,
12541 DMA_CHANNEL channel ,
12542 uint8_t pattern ) ;
12573 DMA_MODULE_ID index ,
12574 DMA_CHANNEL channel ) ;
12606 DMA_MODULE_ID index ) ;
12631 DMA_MODULE_ID index ) ;
12655 DMA_MODULE_ID index ) ;
12680 DMA_MODULE_ID index ) ;
12703 DMA_MODULE_ID index ) ;
12727 DMA_MODULE_ID index ) ;
12750 DMA_MODULE_ID index ) ;
12774 DMA_MODULE_ID index ) ;
12798 DMA_MODULE_ID index ) ;
12823 DMA_MODULE_ID index ) ;
12847 DMA_MODULE_ID index ) ;
12871 DMA_MODULE_ID index ) ;
12894 DMA_MODULE_ID index ) ;
12918 DMA_MODULE_ID index ) ;
12942 DMA_MODULE_ID index ) ;
12966 DMA_MODULE_ID index ) ;
12990 DMA_MODULE_ID index ) ;
13014 DMA_MODULE_ID index ) ;
13037 DMA_MODULE_ID index ) ;
13062 DMA_MODULE_ID index ) ;
13087 DMA_MODULE_ID index ) ;
13111 DMA_MODULE_ID index ) ;
13136 DMA_MODULE_ID index ) ;
13160 DMA_MODULE_ID index ) ;
13184 DMA_MODULE_ID index ) ;
13210 DMA_MODULE_ID index ) ;
13235 DMA_MODULE_ID index ) ;
13259 DMA_MODULE_ID index ) ;
13284 DMA_MODULE_ID index ) ;
13307 DMA_MODULE_ID index ) ;
13330 DMA_MODULE_ID index ) ;
13353 DMA_MODULE_ID index ) ;
13376 DMA_MODULE_ID index ) ;
13401 DMA_MODULE_ID index ) ;
13426 DMA_MODULE_ID index ) ;
13450 DMA_MODULE_ID index ) ;
13475 DMA_MODULE_ID index ) ;
13499 DMA_MODULE_ID index ) ;
13523 DMA_MODULE_ID index ) ;
13546 DMA_MODULE_ID index ) ;
13569 DMA_MODULE_ID index ) ;
13593 DMA_MODULE_ID index ) ;
13617 DMA_MODULE_ID index ) ;
13641 DMA_MODULE_ID index ) ;
13668 #define DMA_CHANNEL_NONE ( ( DMA_CHANNEL ) - 1 ) 13681 #define DMA_CHANNEL_ANY ( ( DMA_CHANNEL ) - 2 ) 13694 #define SYS_DMA_CHANNEL_COUNT DMA_NUMBER_OF_CHANNELS 13724 #define SYS_DMA_CHANNEL_HANDLE_INVALID ( ( SYS_DMA_CHANNEL_HANDLE ) ( - 1 ) ) 13898 DMA_CRC_TYPE type ;
13904 uint8_t polyLength ;
13907 DMA_CRC_BIT_ORDER bitOrder ;
13910 DMA_CRC_BYTE_ORDER byteOrder ;
13920 uint32_t xorBitMask ;
14045 SYS_MODULE_OBJ
object ,
14046 DMA_CHANNEL activeChannel ) ;
14049 #define SYS_DMA_TasksISR( object , activeChannel ) SYS_DMA_Tasks ( object , activeChannel ) 14094 uintptr_t contextHandle ) ;
14140 const SYS_MODULE_INIT *
const init ) ;
14191 DMA_CHANNEL channel ) ;
14277 DMA_TRIGGER_SOURCE eventSrc ) ;
14355 DMA_PATTERN_LENGTH length ,
14357 uint8_t ignorePattern ) ;
14610 const void * srcAddr ,
14612 const void * destAddr ,
14614 size_t cellSize ) ;
14711 const void * srcAddr ,
14713 const void * destAddr ,
14715 size_t cellSize ) ;
14911 const uintptr_t contextHandle ) ;
15207 DMA_TRIGGER_SOURCE eventSrc ) ;
15386 SYS_MODULE_OBJ
object ,
15387 DMA_CHANNEL activeChannel ) ;
15397 SYS_MODULE_OBJ
object ) ;
15407 SYS_MODULE_OBJ
object ,
15408 DMA_CHANNEL activeChannel ) ;
15435 #define DRV_USART_INDEX_0 0 15436 #define DRV_USART_INDEX_1 1 15437 #define DRV_USART_INDEX_2 2 15438 #define DRV_USART_INDEX_3 3 15439 #define DRV_USART_INDEX_4 4 15440 #define DRV_USART_INDEX_5 5 15454 #define DRV_USART_COUNT USART_NUMBER_OF_MODULES 15465 #define DRV_USART_WRITE_ERROR ( ( uint32_t ) ( - 1 ) ) 15476 #define DRV_USART_READ_ERROR ( ( uint32_t ) ( - 1 ) ) 15510 #define DRV_USART_BUFFER_HANDLE_INVALID ( ( DRV_USART_BUFFER_HANDLE ) ( - 1 ) ) 15661 uintptr_t context ) ;
15709 USART_HANDSHAKE_MODE_FLOW_CONTROL
15713 USART_HANDSHAKE_MODE_SIMPLEX
15875 } AddressedModeInit ;
15900 = USART_ERROR_PARITY
15905 = USART_ERROR_FRAMING
15910 = USART_ERROR_RECEIVER_OVERRUN
15992 SYS_MODULE_INIT moduleInit ;
15996 USART_MODULE_ID usartID ;
16014 uint32_t brgClock ;
16030 USART_OPERATION_MODE linesEnable ;
16034 INT_SOURCE interruptTransmit ;
16038 INT_SOURCE interruptReceive ;
16042 INT_SOURCE interruptError ;
16047 unsigned int queueSizeReceive ;
16052 unsigned int queueSizeTransmit ;
16056 DMA_CHANNEL dmaChannelTransmit ;
16060 DMA_CHANNEL dmaChannelReceive ;
16064 INT_SOURCE dmaInterruptTransmit ;
16068 INT_SOURCE dmaInterruptReceive ;
16152 const SYS_MODULE_INDEX index ,
16153 const SYS_MODULE_INIT *
const init ) ;
16191 SYS_MODULE_OBJ
object ) ;
16229 SYS_MODULE_OBJ
object ) ;
16270 SYS_MODULE_OBJ
object ) ;
16311 SYS_MODULE_OBJ
object ) ;
16352 SYS_MODULE_OBJ
object ) ;
16431 const SYS_MODULE_INDEX index ,
16615 const size_t size ) ;
16808 const size_t size ) ;
16896 const uintptr_t context ) ;
17163 const size_t numbytes ) ;
17231 const size_t numbytes ) ;
17368 const uint8_t byte ) ;
17586 const SYS_MODULE_INDEX index ,
17639 const SYS_MODULE_INDEX index ,
17688 const SYS_MODULE_INDEX index ,
17903 #ifndef _DRV_USART_FEATURE_MAPPING_H 17904 #define _DRV_USART_FEATURE_MAPPING_H 17913 #define _DRV_USART_InterruptSourceIsEnabled( source ) false 17914 #define _DRV_USART_InterruptSourceEnable( source ) 17915 #define _DRV_USART_InterruptSourceDisable( source ) false 17916 #define _DRV_USART_InterruptSourceStatusClear( source ) SYS_INT_SourceStatusClear ( source ) 17917 #define _DRV_USART_SEM_POST( x ) OSAL_SEM_Post ( x ) 17918 #define _DRV_USART_TAKE_MUTEX( x , y ) OSAL_MUTEX_Lock ( x , y ) 17919 #define _DRV_USART_RELEASE_MUTEX( x ) OSAL_MUTEX_Unlock ( x ) 17920 #define _SYS_DMA_ChannelForceStart( channelHandle ) SYS_DMA_ChannelForceStart ( channelHandle ) 17923 #define _DRV_USART_ALWAYS_NON_BLOCKING ( DRV_IO_INTENT_NONBLOCKING ) 17932 #define _DRV_USART_TRANSMIT_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteTransmitTasks ( x ) 17933 #define _DRV_USART_RECEIVE_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteReceiveTasks ( x ) 17934 #define _DRV_USART_ERROR_TASKS( x ) _DRV_USART_ByteErrorTasks ( x ) 17935 #define _DRV_USART_CLIENT_BUFFER_QUEUE_OBJECTS_REMOVE( x ) true 17936 #define _DRV_USART_ByteModelInterruptSourceEnable( source ) 17949 #include "system/clk/sys_clk.h" 17950 #include "system/int/sys_int.h" 17988 #ifndef _SYS_DEBUG_H 17989 #define _SYS_DEBUG_H 17990 #include "C:\microchip\harmony\v2_06\framework\system\system.h" 17993 #define SYS_DEBUG_BUFFER_DMA_READY 18043 #define SYS_DEBUG_INDEX_0 0 18059 SYS_MODULE_INIT moduleInit ;
18063 SYS_MODULE_INDEX consoleIndex ;
18111 const SYS_MODULE_INDEX index ,
18112 const SYS_MODULE_INIT *
const init ) ;
18152 SYS_MODULE_OBJ
object ,
18153 const SYS_MODULE_INIT *
const init ) ;
18183 SYS_MODULE_OBJ
object ) ;
18216 SYS_MODULE_OBJ
object ) ;
18260 SYS_MODULE_OBJ
object ) ;
18303 const char * message ) ;
18353 const char * format ,
18443 #define _SYS_DEBUG_MESSAGE( level , message ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Message ( message ) ; } while ( 0 ) 18487 #define _SYS_DEBUG_PRINT( level , format ,... ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Print ( format , ## __VA_ARGS__ ) ; } while ( 0 ) 18530 #define SYS_MESSAGE( message ) 18563 #define SYS_DEBUG_MESSAGE( level , message ) 18610 #define SYS_PRINT( fmt ,... ) 18658 #define SYS_DEBUG_PRINT( level , fmt ,... ) 18683 #define SYS_DEBUG_BreakPoint( ) 18692 #define SYS_DEBUG( level , message ) SYS_DEBUG_MESSAGE ( level , message ) 18693 #define SYS_ERROR( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18694 #define SYS_ERROR_PRINT( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18711 #define _DRV_USART_RX_DEPTH 9 18777 const SYS_MODULE_INDEX index ,
18802 const uint8_t byte ) ;
18873 #ifndef _SYS_PORTS_H 18874 #define _SYS_PORTS_H 18913 #ifndef _SYS_PORTS_DEFINITIONS_H 18914 #define _SYS_PORTS_DEFINITIONS_H 18920 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 18921 #include "system/common/sys_common.h" 18922 #include "system/common/sys_module.h" 18959 #ifndef _PLIB_PORTS_H 18960 #define _PLIB_PORTS_H 18961 #include <stdint.h> 18962 #include <stddef.h> 19027 #ifndef _PLIB_PORTS_PROCESSOR_H 19028 #define _PLIB_PORTS_PROCESSOR_H 19029 #error "Can't find header" 19079 PORTS_MODULE_ID index ,
19080 PORTS_REMAP_INPUT_FUNCTION inputFunction ,
19081 PORTS_REMAP_INPUT_PIN remapInputPin ) ;
19124 PORTS_MODULE_ID index ,
19125 PORTS_REMAP_OUTPUT_FUNCTION outputFunction ,
19126 PORTS_REMAP_OUTPUT_PIN remapOutputPin ) ;
19161 PORTS_MODULE_ID index ,
19162 PORTS_ANALOG_PIN pin ,
19163 PORTS_PIN_MODE mode ) ;
19203 PORTS_MODULE_ID index ,
19204 PORTS_CHANNEL channel ,
19205 PORTS_BIT_POS bitPos ,
19206 PORTS_PIN_MODE mode ) ;
19241 PORTS_MODULE_ID index ,
19242 PORTS_CHANNEL channel ,
19243 PORTS_BIT_POS bitPos ) ;
19277 PORTS_MODULE_ID index ,
19278 PORTS_CHANNEL channel ,
19279 PORTS_BIT_POS bitPos ) ;
19316 PORTS_MODULE_ID index ,
19317 PORTS_CHANNEL channel ,
19318 PORTS_BIT_POS bitPos ) ;
19359 PORTS_MODULE_ID index ,
19360 PORTS_CHANNEL channel ,
19361 PORTS_BIT_POS bitPos ) ;
19400 PORTS_MODULE_ID index ,
19401 PORTS_CHANNEL channel ,
19402 PORTS_BIT_POS bitPos ) ;
19440 PORTS_MODULE_ID index ,
19441 PORTS_CHANNEL channel ,
19442 PORTS_BIT_POS bitPos ) ;
19477 PORTS_MODULE_ID index ,
19478 PORTS_CHANNEL channel ) ;
19513 PORTS_MODULE_ID index ,
19514 PORTS_CHANNEL channel ) ;
19551 PORTS_MODULE_ID index ,
19552 PORTS_CHANNEL channel ) ;
19589 PORTS_MODULE_ID index ,
19590 PORTS_CHANNEL channel ) ;
19627 PORTS_MODULE_ID index ,
19628 PORTS_CHANNEL channel ,
19629 PORTS_BIT_POS bitPos ) ;
19666 PORTS_MODULE_ID index ,
19667 PORTS_CHANNEL channel ,
19668 PORTS_BIT_POS bitPos ) ;
19706 PORTS_MODULE_ID index ,
19707 PORTS_CHANNEL channel ,
19708 PORTS_BIT_POS bitPos ) ;
19745 PORTS_MODULE_ID index ,
19746 PORTS_CHANNEL channel ,
19747 PORTS_BIT_POS bitPos ,
19782 PORTS_MODULE_ID index ,
19783 PORTS_CHANNEL channel ,
19784 PORTS_BIT_POS bitPos ) ;
19818 PORTS_MODULE_ID index ,
19819 PORTS_CHANNEL channel ,
19820 PORTS_BIT_POS bitPos ) ;
19854 PORTS_MODULE_ID index ,
19855 PORTS_CHANNEL channel ,
19856 PORTS_BIT_POS bitPos ) ;
19891 PORTS_MODULE_ID index ,
19892 PORTS_CHANNEL channel ,
19893 PORTS_BIT_POS bitPos ) ;
19928 PORTS_MODULE_ID index ,
19929 PORTS_CHANNEL channel ,
19930 PORTS_BIT_POS bitPos ) ;
19964 PORTS_MODULE_ID index ,
19965 PORTS_CHANNEL channel ,
19966 PORTS_BIT_POS bitPos ) ;
20000 PORTS_MODULE_ID index ,
20001 PORTS_CHANNEL channel ,
20002 PORTS_BIT_POS bitPos ) ;
20040 PORTS_MODULE_ID index ,
20041 PORTS_CHANNEL channel ) ;
20075 PORTS_MODULE_ID index ,
20076 PORTS_CHANNEL channel ) ;
20110 PORTS_MODULE_ID index ,
20111 PORTS_CHANNEL channel ,
20154 PORTS_MODULE_ID index ,
20155 PORTS_CHANNEL channel ,
20191 PORTS_MODULE_ID index ,
20192 PORTS_CHANNEL channel ,
20227 PORTS_MODULE_ID index ,
20228 PORTS_CHANNEL channel ,
20264 PORTS_MODULE_ID index ,
20265 PORTS_CHANNEL channel ,
20300 PORTS_MODULE_ID index ,
20301 PORTS_CHANNEL channel ,
20334 PORTS_MODULE_ID index ,
20335 PORTS_CHANNEL channel ) ;
20369 PORTS_MODULE_ID index ,
20370 PORTS_CHANNEL channel ,
20406 PORTS_MODULE_ID index ,
20407 PORTS_CHANNEL channel ,
20453 PORTS_MODULE_ID index ,
20454 PORTS_CHANNEL channel ,
20456 PORTS_PIN_MODE mode ) ;
20498 PORTS_MODULE_ID index ,
20499 PORTS_CHANNEL channel ,
20542 PORTS_MODULE_ID index ,
20543 PORTS_CHANNEL channel ,
20583 PORTS_MODULE_ID index ,
20584 PORTS_CHANNEL channel ,
20624 PORTS_MODULE_ID index ,
20625 PORTS_CHANNEL channel ,
20669 PORTS_MODULE_ID index ,
20670 PORTS_CHANNEL channel ,
20714 PORTS_MODULE_ID index ,
20715 PORTS_CHANNEL channel ,
20761 PORTS_MODULE_ID index ,
20762 PORTS_AN_PIN anPins ,
20763 PORTS_PIN_MODE mode ) ;
20806 PORTS_MODULE_ID index ,
20807 PORTS_CN_PIN cnPins ) ;
20851 PORTS_MODULE_ID index ,
20852 PORTS_CN_PIN cnPins ) ;
20895 PORTS_MODULE_ID index ,
20896 PORTS_CN_PIN cnPins ) ;
20939 PORTS_MODULE_ID index ,
20940 PORTS_CN_PIN cnPins ) ;
20974 PORTS_MODULE_ID index ) ;
21007 PORTS_MODULE_ID index ) ;
21043 PORTS_MODULE_ID index ,
21044 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
21080 PORTS_MODULE_ID index ,
21081 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
21118 PORTS_MODULE_ID index ) ;
21152 PORTS_MODULE_ID index ) ;
21188 PORTS_MODULE_ID index ,
21189 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
21225 PORTS_MODULE_ID index ,
21226 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
21271 PORTS_MODULE_ID index ,
21272 PORTS_CHANNEL channel ,
21274 PORTS_PIN_SLEW_RATE slewRate ) ;
21311 PORTS_PIN_SLEW_RATE
21313 PORTS_MODULE_ID index ,
21314 PORTS_CHANNEL channel ,
21315 PORTS_BIT_POS bitPos ) ;
21354 PORTS_MODULE_ID index ,
21355 PORTS_CHANNEL channel ,
21356 PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod ) ;
21389 PORTS_CHANGE_NOTICE_METHOD
21391 PORTS_MODULE_ID index ,
21392 PORTS_CHANNEL channel ) ;
21440 PORTS_MODULE_ID index ,
21441 PORTS_CHANNEL channel ,
21491 PORTS_MODULE_ID index ,
21492 PORTS_CHANNEL channel ,
21540 PORTS_MODULE_ID index ,
21541 PORTS_CHANNEL channel ,
21542 PORTS_BIT_POS bitPos ,
21543 PORTS_CHANGE_NOTICE_EDGE cnEdgeType ) ;
21586 PORTS_MODULE_ID index ,
21587 PORTS_CHANNEL channel ,
21588 PORTS_BIT_POS bitPos ) ;
21619 PORTS_MODULE_ID index ) ;
21643 PORTS_MODULE_ID index ) ;
21667 PORTS_MODULE_ID index ) ;
21691 PORTS_MODULE_ID index ) ;
21716 PORTS_MODULE_ID index ) ;
21741 PORTS_MODULE_ID index ) ;
21772 PORTS_MODULE_ID index ) ;
21800 PORTS_MODULE_ID index ) ;
21827 PORTS_MODULE_ID index ) ;
21852 PORTS_MODULE_ID index ) ;
21879 PORTS_MODULE_ID index ) ;
21904 PORTS_MODULE_ID index ) ;
21931 PORTS_MODULE_ID index ) ;
21956 PORTS_MODULE_ID index ) ;
21984 PORTS_MODULE_ID index ) ;
22012 PORTS_MODULE_ID index ) ;
22040 PORTS_MODULE_ID index ) ;
22066 PORTS_MODULE_ID index ) ;
22092 PORTS_MODULE_ID index ) ;
22118 PORTS_MODULE_ID index ) ;
22143 PORTS_MODULE_ID index ) ;
22169 PORTS_MODULE_ID index ) ;
22196 PORTS_MODULE_ID index ) ;
22221 PORTS_MODULE_ID index ) ;
22256 #ifndef _PLIB_PORTS_COMPATIBILITY_H 22257 #define _PLIB_PORTS_COMPATIBILITY_H 22258 #include <stdint.h> 22259 #include <stddef.h> 22294 #define PLIB_PORTS_ChangeNoticePerPortHasOccured PLIB_PORTS_ChangeNoticePerPortHasOccurred 22311 #include "system/int/sys_int.h" 22445 PORTS_MODULE_ID index ,
22446 PORTS_CHANNEL channel ) ;
22478 PORTS_MODULE_ID index ,
22479 PORTS_CHANNEL channel ,
22509 PORTS_MODULE_ID index ,
22510 PORTS_CHANNEL channel ) ;
22548 PORTS_MODULE_ID index ,
22549 PORTS_CHANNEL channel ,
22583 PORTS_MODULE_ID index ,
22584 PORTS_CHANNEL channel ,
22621 PORTS_MODULE_ID index ,
22623 PORTS_CHANNEL channel ,
22653 PORTS_MODULE_ID index ,
22654 PORTS_CHANNEL channel ) ;
22685 PORTS_MODULE_ID index ,
22686 PORTS_CHANNEL channel ,
22718 PORTS_MODULE_ID index ,
22719 PORTS_CHANNEL channel ,
22751 PORTS_MODULE_ID index ,
22752 PORTS_CHANNEL channel ,
22786 PORTS_MODULE_ID index ,
22787 PORTS_CHANNEL channel ) ;
22827 PORTS_MODULE_ID index ,
22828 PORTS_REMAP_INPUT_FUNCTION
function ,
22829 PORTS_REMAP_INPUT_PIN remapPin ) ;
22864 PORTS_MODULE_ID index ,
22865 PORTS_REMAP_OUTPUT_FUNCTION
function ,
22866 PORTS_REMAP_OUTPUT_PIN remapPin ) ;
22899 PORTS_MODULE_ID index ) ;
22927 PORTS_MODULE_ID index ) ;
22961 PORTS_MODULE_ID index ,
22962 PORTS_CHANGE_NOTICE_PIN pinNum ,
22994 PORTS_MODULE_ID index ,
22995 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
23024 PORTS_MODULE_ID index ) ;
23053 PORTS_MODULE_ID index ) ;
23084 PORTS_MODULE_ID index ,
23085 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
23116 PORTS_MODULE_ID index ,
23117 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
23156 PORTS_MODULE_ID index ,
23157 PORTS_ANALOG_PIN pin ,
23158 PORTS_PIN_MODE mode ) ;
23195 PORTS_MODULE_ID index ,
23196 PORTS_CHANNEL channel ,
23197 PORTS_BIT_POS bitPos ,
23232 PORTS_MODULE_ID index ,
23233 PORTS_CHANNEL channel ,
23234 PORTS_BIT_POS bitPos ) ;
23267 PORTS_MODULE_ID index ,
23268 PORTS_CHANNEL channel ,
23269 PORTS_BIT_POS bitPos ) ;
23302 PORTS_MODULE_ID index ,
23303 PORTS_CHANNEL channel ,
23304 PORTS_BIT_POS bitPos ) ;
23337 PORTS_MODULE_ID index ,
23338 PORTS_CHANNEL channel ,
23339 PORTS_BIT_POS bitPos ) ;
23372 PORTS_MODULE_ID index ,
23373 PORTS_CHANNEL channel ,
23374 PORTS_BIT_POS bitPos ) ;
23411 PORTS_MODULE_ID index ,
23413 PORTS_CHANNEL channel ,
23414 PORTS_BIT_POS bitPos ) ;
23447 PORTS_MODULE_ID index ,
23448 PORTS_CHANNEL channel ,
23449 PORTS_BIT_POS bitPos ) ;
23482 PORTS_MODULE_ID index ,
23483 PORTS_CHANNEL channel ,
23484 PORTS_BIT_POS bitPos ) ;
23517 PORTS_MODULE_ID index ,
23518 PORTS_CHANNEL channel ,
23519 PORTS_BIT_POS bitPos ) ;
23552 PORTS_MODULE_ID index ,
23553 PORTS_CHANNEL channel ,
23554 PORTS_BIT_POS bitPos ) ;
23587 PORTS_MODULE_ID index ,
23588 PORTS_CHANNEL channel ,
23589 PORTS_BIT_POS bitPos ) ;
23622 PORTS_MODULE_ID index ,
23623 PORTS_CHANNEL channel ,
23624 PORTS_BIT_POS bitPos ) ;
23657 PORTS_MODULE_ID index ,
23658 PORTS_CHANNEL channel ,
23659 PORTS_BIT_POS bitPos ,
23742 #ifndef _DRV_SPI_DEFINITIONS_H 23743 #define _DRV_SPI_DEFINITIONS_H 23749 #include <stdint.h> 23750 #include <stdbool.h> 23751 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 23752 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 23788 #ifndef _PLIB_SPI_H 23789 #define _PLIB_SPI_H 23823 #ifndef _PLIB_SPI_PROCESSOR_H 23824 #define _PLIB_SPI_PROCESSOR_H 23825 #error "Can't find header" 23870 SPI_MODULE_ID index ) ;
23900 SPI_MODULE_ID index ) ;
23932 SPI_MODULE_ID index ) ;
23964 SPI_MODULE_ID index ) ;
23998 SPI_MODULE_ID index ) ;
24028 SPI_MODULE_ID index ) ;
24065 SPI_MODULE_ID index ) ;
24104 SPI_MODULE_ID index ) ;
24134 SPI_MODULE_ID index ,
24165 SPI_MODULE_ID index ,
24199 SPI_MODULE_ID index ,
24200 SPI_COMMUNICATION_WIDTH width ) ;
24235 SPI_MODULE_ID index ,
24236 SPI_AUDIO_COMMUNICATION_WIDTH mode ) ;
24268 SPI_MODULE_ID index ,
24269 SPI_INPUT_SAMPLING_PHASE phase ) ;
24301 SPI_MODULE_ID index ,
24302 SPI_OUTPUT_DATA_PHASE phase ) ;
24333 SPI_MODULE_ID index ,
24334 SPI_CLOCK_POLARITY polarity ) ;
24364 SPI_MODULE_ID index ) ;
24394 SPI_MODULE_ID index ) ;
24432 SPI_MODULE_ID index ,
24433 uint32_t clockFrequency ,
24434 uint32_t baudRate ) ;
24465 SPI_MODULE_ID index ) ;
24497 SPI_MODULE_ID index ) ;
24530 SPI_MODULE_ID index ) ;
24563 SPI_MODULE_ID index ) ;
24595 SPI_MODULE_ID index ) ;
24625 SPI_MODULE_ID index ) ;
24656 SPI_MODULE_ID index ) ;
24687 SPI_MODULE_ID index ) ;
24718 SPI_MODULE_ID index ) ;
24750 SPI_MODULE_ID index ,
24751 SPI_FIFO_TYPE type ) ;
24783 SPI_MODULE_ID index ) ;
24815 SPI_MODULE_ID index ) ;
24849 SPI_MODULE_ID index ,
24850 SPI_FIFO_INTERRUPT mode ) ;
24880 SPI_MODULE_ID index ) ;
24910 SPI_MODULE_ID index ) ;
24942 SPI_MODULE_ID index ,
24943 SPI_FRAME_PULSE_DIRECTION direction ) ;
24976 SPI_MODULE_ID index ,
24977 SPI_FRAME_PULSE_POLARITY polarity ) ;
25010 SPI_MODULE_ID index ,
25011 SPI_FRAME_PULSE_EDGE edge ) ;
25044 SPI_MODULE_ID index ,
25045 SPI_FRAME_PULSE_WIDTH width ) ;
25079 SPI_MODULE_ID index ,
25080 SPI_FRAME_SYNC_PULSE pulse ) ;
25112 SPI_MODULE_ID index ) ;
25142 SPI_MODULE_ID index ) ;
25174 SPI_MODULE_ID index ) ;
25204 SPI_MODULE_ID index ) ;
25234 SPI_MODULE_ID index ) ;
25264 SPI_MODULE_ID index ) ;
25295 SPI_MODULE_ID index ,
25327 SPI_MODULE_ID index ,
25359 SPI_MODULE_ID index ,
25382 SPI_MODULE_ID index ) ;
25413 SPI_MODULE_ID index ,
25414 SPI_BAUD_RATE_CLOCK type ) ;
25446 SPI_MODULE_ID index ,
25447 SPI_ERROR_INTERRUPT error ) ;
25479 SPI_MODULE_ID index ,
25480 SPI_ERROR_INTERRUPT error ) ;
25511 SPI_MODULE_ID index ,
25512 SPI_AUDIO_ERROR error ) ;
25543 SPI_MODULE_ID index ,
25544 SPI_AUDIO_ERROR error ) ;
25574 SPI_MODULE_ID index ) ;
25604 SPI_MODULE_ID index ) ;
25636 SPI_MODULE_ID index ,
25637 SPI_AUDIO_TRANSMIT_MODE mode ) ;
25669 SPI_MODULE_ID index ,
25670 SPI_AUDIO_PROTOCOL mode ) ;
25703 SPI_MODULE_ID index ) ;
25729 SPI_MODULE_ID index ) ;
25755 SPI_MODULE_ID index ) ;
25780 SPI_MODULE_ID index ) ;
25805 SPI_MODULE_ID index ) ;
25830 SPI_MODULE_ID index ) ;
25856 SPI_MODULE_ID index ) ;
25881 SPI_MODULE_ID index ) ;
25906 SPI_MODULE_ID index ) ;
25931 SPI_MODULE_ID index ) ;
25956 SPI_MODULE_ID index ) ;
25981 SPI_MODULE_ID index ) ;
26007 SPI_MODULE_ID index ) ;
26032 SPI_MODULE_ID index ) ;
26057 SPI_MODULE_ID index ) ;
26082 SPI_MODULE_ID index ) ;
26108 SPI_MODULE_ID index ) ;
26134 SPI_MODULE_ID index ) ;
26160 SPI_MODULE_ID index ) ;
26184 SPI_MODULE_ID index ) ;
26209 SPI_MODULE_ID index ) ;
26234 SPI_MODULE_ID index ) ;
26259 SPI_MODULE_ID index ) ;
26285 SPI_MODULE_ID index ) ;
26310 SPI_MODULE_ID index ) ;
26335 SPI_MODULE_ID index ) ;
26360 SPI_MODULE_ID index ) ;
26385 SPI_MODULE_ID index ) ;
26410 SPI_MODULE_ID index ) ;
26436 SPI_MODULE_ID index ) ;
26463 SPI_MODULE_ID index ) ;
26488 SPI_MODULE_ID index ) ;
26514 SPI_MODULE_ID index ) ;
26540 SPI_MODULE_ID index ) ;
26566 SPI_MODULE_ID index ) ;
26591 SPI_MODULE_ID index ) ;
26616 SPI_MODULE_ID index ) ;
26642 SPI_MODULE_ID index ) ;
26668 SPI_MODULE_ID index ) ;
26680 #include "system/common/sys_common.h" 26681 #include "system/common/sys_module.h" 26682 #include "system/int/sys_int.h" 26683 #include "system/clk/sys_clk.h" 26684 #include "C:\microchip\harmony\v2_06\framework\system\ports\sys_ports.h" 26722 #define DRV_SPI_BUFFER_HANDLE_INVALID ( ( DRV_SPI_BUFFER_HANDLE ) ( - 1 ) ) 26734 #define DRV_SPI_INDEX_0 0 26735 #define DRV_SPI_INDEX_1 1 26736 #define DRV_SPI_INDEX_2 2 26737 #define DRV_SPI_INDEX_3 3 26738 #define DRV_SPI_INDEX_4 4 26739 #define DRV_SPI_INDEX_5 5 26751 #define DRV_SPI_INDEX_COUNT SPI_NUMBER_OF_MODULES 27000 SPI_MODULE_ID
spiId ;
27033 CLK_BUSES_PERIPHERAL
spiClk ;
27193 const SYS_MODULE_INDEX index ,
27194 const SYS_MODULE_INIT *
const init ) ;
27236 SYS_MODULE_OBJ
object ) ;
27285 SYS_MODULE_OBJ
object ) ;
27326 SYS_MODULE_OBJ
object ) ;
27391 const SYS_MODULE_INDEX drvIndex ,
27986 #include "driver/usb/usbhs/drv_usbhs.h" 27987 #include "usb/usb_device.h" 28015 #include <stdint.h> 28035 uint8_t RevNumber ;
28122 SYS_MODULE_OBJ sysTmr ;
28123 SYS_MODULE_OBJ drvTmr0 ;
28124 SYS_MODULE_OBJ drvTmr1 ;
28125 SYS_MODULE_OBJ drvTmr2 ;
28126 SYS_MODULE_OBJ drvTmr3 ;
28127 SYS_MODULE_OBJ drvTmr4 ;
28128 SYS_MODULE_OBJ drvUsart0 ;
28129 SYS_MODULE_OBJ drvPMP0 ;
28131 SYS_MODULE_OBJ spiObjectIdx0 ;
28133 SYS_MODULE_OBJ spiObjectIdx1 ;
28135 SYS_MODULE_OBJ spiObjectIdx2 ;
28136 SYS_MODULE_OBJ drvUSBObject ;
28137 SYS_MODULE_OBJ usbDevObject0 ;
28201 uint8_t null_count ;
28202 bool send_message_complete_flag ;
28209 uint8_t table_count ;
28221 uint8_t byte [ 4 ] ;
28241 uint8_t identifier ;
28243 uint8_t msg_length ;
28244 uint8_t xmit_ready_flag ;
28329 static const uint8_t
28331 { 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U ,
28332 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U
28333 , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U ,
28334 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U
28335 , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U ,
28336 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U
28337 , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U ,
28338 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU
28339 , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU ,
28340 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U
28341 , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U } ;
28343 static const uint8_t
28345 { 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U ,
28346 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U
28347 , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U ,
28348 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U
28349 , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U ,
28350 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U } ;
28386 uint8_t Identifier ,
28388 uint8_t Msg_Length ) ;
28578 #include <stdint.h> 28584 #define bitset( var , bitno ) ( ( var ) |= 1UL << ( bitno ) ) 28585 #define bitclr( var , bitno ) ( ( var ) &= ~ ( 1UL << ( bitno ) ) ) 28608 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 28)));
28611 ( bitposn - 1U ) ) ) ;
28628 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 30)));
28631 ( bitposn - 1U ) ) ) ) ;
28650 int izzqqzz=((int)(
bitmapstruct.element2 |= (1 << 0)));
28655 a_temp[ 0 ] = byte ;
28656 a_temp[ 1 ] = ( uint8_t ) (
28658 a_temp[ 2 ] = ( uint8_t ) (
PIB_Status & 0x00FFU ) ;
28659 a_temp[ 3 ] = ( uint8_t ) (
28660 ( data2 & 0x0FF0U ) >> 4 ) ;
28661 a_temp[ 4 ] = ( uint8_t ) (
28662 ( data2 & 0x000FU ) ) << 4 ;
28663 a_temp[ 4 ] = a_temp[ 4 ] | ( uint8_t ) (
28664 ( data1 & 0x0F00U ) >> 8 ) ;
28665 a_temp[ 5 ] = ( uint8_t ) ( data1 & 0x00FFU ) ;
28692 int izzqqzz=((int)(
bitmapstruct.element2 |= (1 << 2)));
28698 b_temp[ 1 ] = ( uint8_t ) (
PIB_Status >> 8 ) ;
28700 b_temp[ 3 ] = ( byt[ 0 ] & 0x07U ) << 5 ;
28703 b_temp[ 3 ] = b_temp[ 3 ] | (
28704 ( byt[ 1 ] ) >> 3 ) ;
28707 b_temp[ 4 ] = ( byt[ 1 ] & 0x07U ) << 5 ;
28710 b_temp[ 4 ] = b_temp[ 4 ] | (
28711 ( byt[ 0 ] >> 4 ) & 0x07U ) ;
28712 b_temp[ 5 ] = byt[ 2 ] ;
28729 #define qqqbranches 68 28730 #define QQQMAXMCDCSIZE 2 28734 #define ldra_sscanf 28750 #undef qqnull_params 28751 #define qqnull_params void 28753 #define qqzzidfield 1 28759 #define QQQFIXEDSIZE 28779 qqcptr = qqscan_str;
28781 while (qqcptr[0] ==
' ')
28787 if (qqcptr[0] ==
'-')
28793 while ((qqcptr[0] >=
'0') && (qqcptr[0] <=
'9'))
28795 qqvalue = 10 * qqvalue;
28796 qqvalue = qqvalue + (qqcptr[0] -
'0');
28799 qqvalue = qqisign * qqvalue;
28825 ldra_sprintf2 (&ldra_buffer[0], s,i,
zzfileid);
28826 ldra_port_write (&ldra_buffer[0]);
28834 ldra_port_write(s);
28842 ldra_sprintf2 (&ldra_buffer[0], s, i, j);
28843 ldra_port_write (&ldra_buffer[0]);
28851 ldra_sprintf3 (&ldra_buffer[0], s, i, j, k);
28852 ldra_port_write (&ldra_buffer[0]);
28860 ldra_sprintf4 (&ldra_buffer[0], s, i, j, k, l);
28861 ldra_port_write (&ldra_buffer[0]);
28980 static int branches_printed = 0;
28984 ldra_sprintf1 (&ldra_buffer[0], s, (i >> last) & ~(~0 << 8));
28985 ldra_port_write (&ldra_buffer[0]);
28986 ldra_sprintf1 (&ldra_buffer[0],
"%8d\n",
zzfileid );
28987 ldra_port_write (&ldra_buffer[0]);
28989 branches_printed += 8;
29009 #define ELEMENT(N) qqbmsoutput("%8d", bitmapstruct.element##N); 29010 #define LASTELEMENT 29011 #include "statusst_58zbelem.def"
void PLIB_DMA_SuspendDisable(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsStopInIdle(DMA_MODULE_ID index)
void SYS_DMA_TasksErrorISR(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
void PLIB_USART_OperationModeSelect(USART_MODULE_ID index, USART_OPERATION_MODE operationmode)
int32_t DRV_SPI_ClientConfigure(DRV_HANDLE handle, const DRV_SPI_CLIENT_DATA *cfgData)
void PLIB_SPI_FrameSyncPulseWidthSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_WIDTH width)
void DRV_USART_WriteByte(const DRV_HANDLE handle, const uint8_t byte)
void PLIB_USART_BaudRateSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
static int statusst_58zqendz(int qqqi)
void PLIB_PORTS_PinChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_PORTS_ExistsPinChangeNotice(PORTS_MODULE_ID index)
void(* DRV_TMR_CALLBACK)(uintptr_t context, uint32_t alarmCount)
bool PLIB_PORTS_ExistsPortsOpenDrain(PORTS_MODULE_ID index)
SPI_BAUD_RATE_CLOCK baudClockSource
bool SYS_DMA_IsBusy(void)
DMA_CHANNEL_INT_SOURCE PLIB_DMA_ChannelXTriggerSourceNumberGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ChannelXCollisionStatus(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_COLLISION collisonType)
int16_t PLIB_USART_Receiver9BitsReceive(USART_MODULE_ID index)
static void Send_Space(void)
void PLIB_PORTS_ChangeNoticePullUpPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_SPI_Close(DRV_HANDLE handle)
uint16_t PLIB_DMA_ChannelXSourceSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
uint8_t PLIB_USART_AddressGet(USART_MODULE_ID index)
void Clear_Status(uint8_t bitposn)
void PLIB_SPI_Disable(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXDestinationStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t destinationStartAddress)
bool PLIB_USART_ExistsReceiverOverrunStatus(USART_MODULE_ID index)
bool PLIB_DMA_ExistsCRC(DMA_MODULE_ID index)
struct _DRV_SPI_INIT DRV_SPI_INIT
static DRV_TMR_OPERATION_MODE DRV_TMR1_OperationModeGet(void)
void SYS_DEBUG_Reinitialize(SYS_MODULE_OBJ object, const SYS_MODULE_INIT *const init)
PORTS_DATA_MASK PLIB_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_PORTS_PinGetLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_PORTS_ExistsChangeNoticeEdgeControl(PORTS_MODULE_ID index)
uint32_t DRV_TMR0_PeriodValueGet(void)
DRV_HANDLE DRV_USART0_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
bool PLIB_DMA_ExistsChannelXPatternData(DMA_MODULE_ID index)
bool PLIB_SPI_TransmitUnderRunStatusGet(SPI_MODULE_ID index)
uint8_t Fifo_Length(TFifo *ptrFifo)
void DRV_TMR0_CounterValueSet(uint32_t value)
bool PLIB_SPI_FrameErrorStatusGet(SPI_MODULE_ID index)
unsigned int DRV_USART_TransmitBufferSizeGet(const DRV_HANDLE handle)
uint16_t PLIB_DMA_ChannelXCellProgressPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
USART_ERROR PLIB_USART_ErrorsGet(USART_MODULE_ID index)
void SYS_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
void PLIB_USART_IrDAEnable(USART_MODULE_ID index)
bool PLIB_SPI_TransmitBufferIsFull(SPI_MODULE_ID index)
void DRV_TMR3_CounterValueSet(uint32_t value)
void PLIB_USART_BRGClockSourceSelect(USART_MODULE_ID index, USART_BRG_CLOCK_SOURCE brgClockSource)
bool PLIB_PORTS_ExistsSlewRateControl(PORTS_MODULE_ID index)
SPI_FRAME_PULSE_POLARITY framePulsePolarity
void PLIB_PORTS_DirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void Prepare_Return_A(uint8_t byte, uint16_t data2, uint16_t data1)
bool SYS_PORTS_PinLatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_ClockPolaritySelect(SPI_MODULE_ID index, SPI_CLOCK_POLARITY polarity)
void SYS_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void PLIB_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_ChannelXSourceStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t sourceStartAddress)
void PLIB_USART_ReceiverAddressDetectDisable(USART_MODULE_ID index)
SYS_STATUS DRV_SPI_Status(SYS_MODULE_OBJ object)
void PLIB_USART_TransmitterBreakSend(USART_MODULE_ID index)
DMA_PATTERN_LENGTH PLIB_DMA_ChannelXPatternLengthGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void DRV_TMR_AlarmPeriodSet(DRV_HANDLE handle, uint32_t value)
uint32_t DRV_TMR0_CounterFrequencyGet(void)
uint32_t PLIB_DMA_RecentAddressAccessed(DMA_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART0_LineControlSet(DRV_USART_LINE_CONTROL lineControlMode)
void PLIB_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
void DRV_TMR0_StopInIdleDisable(void)
ldra_void_function qqqaccumupload[QQQnumfil]
void PLIB_PORTS_ChangeNoticePullUpPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_DMA_ERROR SYS_DMA_ChannelErrorGet(SYS_DMA_CHANNEL_HANDLE handle)
void SYS_DEBUG_Tasks(SYS_MODULE_OBJ object)
void PLIB_SPI_ErrorInterruptEnable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
bool PLIB_PORTS_PinGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_USART0_WriteByte(const uint8_t byte)
void Generate_Sine_Wave_Data(float32_t NoOfTicks)
void PLIB_DMA_CRCAppendModeEnable(DMA_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT
TMR_PRESCALE DRV_TMR4_PrescalerGet(void)
void PLIB_SPI_StopInIdleEnable(SPI_MODULE_ID index)
static struct bitmapstruct_t bitmapstruct
void DRV_TMR0_StopInIdleEnable(void)
void DRV_TMR1_PeriodValueSet(uint32_t value)
void PLIB_PORTS_CnPinsPullUpDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
bool PLIB_SPI_Exists32bitBuffer(SPI_MODULE_ID index)
void PLIB_PORTS_PinDirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_DMA_CHANNEL_HANDLE SYS_DMA_ChannelAllocate(DMA_CHANNEL channel)
bool PLIB_USART_ExistsLineControlMode(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternIgnore(DMA_MODULE_ID index)
void DRV_TMR0_CounterClear(void)
void DRV_IC_Stop(DRV_HANDLE handle)
void(* SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER)(SYS_DMA_TRANSFER_EVENT event, SYS_DMA_CHANNEL_HANDLE handle, uintptr_t contextHandle)
void DRV_TMR4_StopInIdleDisable(void)
void PLIB_PORTS_ChannelChangeNoticeEdgeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
static void DRV_TMR4_Tasks(void)
void SYS_DMA_Suspend(void)
bool PLIB_DMA_LastBusAccessIsRead(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsCRCPolynomialLength(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsCRCChannel(DMA_MODULE_ID index)
bool PLIB_USART_ExistsTransmitter9BitsSend(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiverEnable(USART_MODULE_ID index)
void SYS_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_MODULE_OBJ SYS_DEBUG_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void PLIB_USART_ReceiverAddressDetectEnable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsAudioErrorControl(SPI_MODULE_ID index)
void SYS_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_USART_BufferAddRead(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *const bufferHandle, void *buffer, const size_t size)
bool DRV_SPIn_ReceiverBufferIsFull(void)
bool PLIB_SPI_ExistsFrameErrorStatus(SPI_MODULE_ID index)
DRV_USART_BAUD_SET_RESULT
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead2(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
void DRV_USART_AddressedBufferAddWrite(const DRV_HANDLE hClient, DRV_USART_BUFFER_HANDLE *bufferHandle, uint8_t address, void *source, size_t nWords)
bool PLIB_SPI_ExistsOutputDataPhase(SPI_MODULE_ID index)
SYS_ERROR_LEVEL gblErrLvl
uint16_t PLIB_DMA_ChannelXDestinationPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void(* DRV_SPI_BUFFER_EVENT_HANDLER)(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
bool PLIB_PORTS_ExistsPortsWrite(PORTS_MODULE_ID index)
PORTS_DATA_MASK SYS_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static void qqoutput(FILEPOINT char *s, int i)
void PLIB_USART_ReceiverEnable(USART_MODULE_ID index)
bool PLIB_DMA_CRCIsEnabled(DMA_MODULE_ID index)
bool PLIB_USART_TransmitterIsEmpty(USART_MODULE_ID index)
static void DRV_TMR4_Open(void)
void DRV_USART_Deinitialize(SYS_MODULE_OBJ object)
bool PLIB_DMA_ExistsRecentAddress(DMA_MODULE_ID index)
void SYS_PORTS_PinPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ReceiverOverrunHasOccurred(USART_MODULE_ID index)
void PLIB_DMA_ChannelXAbortIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQ)
bool PLIB_PORTS_ExistsPinChangeNoticePerPort(PORTS_MODULE_ID index)
bool PLIB_DMA_ChannelXAutoIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint8_t jobQueueReserveSize
bool PLIB_SPI_ExistsErrorInterruptControl(SPI_MODULE_ID index)
bool PLIB_USART_ExistsReceiverInterruptMode(USART_MODULE_ID index)
void SYS_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void DRV_TMR2_StopInIdleDisable(void)
DRV_HANDLE DRV_USART_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
SYS_MODULE_INIT moduleInit
void DRV_ADC_DeInitialize(void)
uint32_t DRV_TMR_AlarmPeriodGet(DRV_HANDLE handle)
void DRV_USART_ByteErrorCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void PLIB_USART_BaudRateHighEnable(USART_MODULE_ID index)
void PLIB_SPI_FramedCommunicationEnable(SPI_MODULE_ID index)
USART_BRG_CLOCK_SOURCE PLIB_USART_BRGClockSourceGet(USART_MODULE_ID index)
void SYS_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXAutoEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_USART_TRANSFER_STATUS DRV_USART_TransferStatus(const DRV_HANDLE handle)
static void qqoutput0(FILEPOINT char *s)
bool PLIB_SPI_ExistsSlaveSelectControl(SPI_MODULE_ID index)
void PLIB_DMA_AbortTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint16_t PLIB_DMA_ChannelXSourcePointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_SPI_BufferWrite(SPI_MODULE_ID index, uint8_t data)
bool PLIB_DMA_ChannelXBusyIsBusy(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsChangeNoticePerPortStatus(PORTS_MODULE_ID index)
void SYS_PORTS_ChangeNotificationDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_USART_ReceiverIsIdle(USART_MODULE_ID index)
PORTS_DATA_TYPE SYS_PORTS_InterruptStatusGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static int qqqisinitialised
bool PLIB_DMA_ExistsCRCType(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseWidth(SPI_MODULE_ID index)
bool PLIB_DMA_ChannelXPatternIgnoreByteIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void Fifo_Init(TFifo *ptrFifo, uint8_t *ptrBuffer, uint16_t Length)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelXPriorityGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsPinControl(SPI_MODULE_ID index)
void PLIB_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void Send_Message_Tasks(void)
uint32_t DRV_TMR3_CounterValueGet(void)
bool PLIB_DMA_CRCAppendModeIsEnabled(DMA_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR0_OperationModeGet(void)
void DRV_TMR4_CounterValueSet(uint32_t value)
SYS_STATUS DRV_USART_Status(SYS_MODULE_OBJ object)
bool PLIB_USART_ExistsReceiverParityErrorStatus(USART_MODULE_ID index)
static void DRV_TMR0_Close(void)
void PLIB_USART_StopInIdleEnable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXAutoDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
uintptr_t SYS_DMA_CHANNEL_HANDLE
bool PLIB_USART_ExistsTransmitterEmptyStatus(USART_MODULE_ID index)
bool DRV_TMR1_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
DMA_DESTINATION_ADDRESSING_MODE PLIB_DMA_ChannelXDestinationAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsAnPinsMode(PORTS_MODULE_ID index)
static void DRV_TMR3_Close(void)
void PLIB_USART_TransmitterIdleIsLowEnable(USART_MODULE_ID index)
void Reset_CRC_Value(void)
DMA_CRC_BYTE_ORDER PLIB_DMA_CRCByteOrderGet(DMA_MODULE_ID index)
INT_SOURCE txInterruptSource
bool PLIB_USART_ExistsReceiverAddressMask(USART_MODULE_ID index)
void PLIB_PORTS_CnPinsPullUpEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void DRV_TMR3_Initialize(void)
void PLIB_USART_ReceiverIdleStateLowEnable(USART_MODULE_ID index)
void PLIB_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint8_t Fifo_Put(TFifo *ptrFifo, uint8_t Data)
void DRV_USART0_Close(void)
void DRV_USART_ByteReceiveCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
size_t SYS_DMA_ChannelDestinationTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
bool DRV_IC0_BufferIsEmpty(void)
bool PLIB_DMA_ExistsChannelXStartIRQ(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXBusyInActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsFIFOInterruptMode(SPI_MODULE_ID index)
bool SYS_DMA_ChannelIsBusy(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_TransmitterIdleIsLowDisable(USART_MODULE_ID index)
void PLIB_SPI_SlaveSelectEnable(SPI_MODULE_ID index)
void SYS_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION function, PORTS_REMAP_OUTPUT_PIN remapPin)
bool PLIB_USART_ExistsReceiver9Bits(USART_MODULE_ID index)
static SYS_STATUS DRV_TMR1_Status(void)
DRV_USART_TRANSFER_STATUS
uint8_t Calc_CRC_Uplink(uint16_t Count, const uint8_t Bytes [])
void PLIB_PORTS_ChangeNoticeInIdleEnable(PORTS_MODULE_ID index)
bool PLIB_USART_ReceiverDataIsAvailable(USART_MODULE_ID index)
void PLIB_SPI_AudioProtocolModeSelect(SPI_MODULE_ID index, SPI_AUDIO_PROTOCOL mode)
void SYS_DMA_TasksError(SYS_MODULE_OBJ object)
uint32_t PLIB_DMA_ChannelXDestinationStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_USART_ReceiverDisable(USART_MODULE_ID index)
SYS_DMA_CHANNEL_IGNORE_MATCH
SPI_FRAME_PULSE_DIRECTION framePulseDirection
void SYS_DEBUG_Deinitialize(SYS_MODULE_OBJ object)
static void DRV_TMR0_DeInitialize(void)
uint32_t DRV_TMR4_PeriodValueGet(void)
void PLIB_PORTS_PinChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
#define statusst_58zqqzqz1
void PLIB_USART_ReceiverOverrunErrorClear(USART_MODULE_ID index)
void * PLIB_USART_ReceiverAddressGet(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXCellProgressPointer(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsReceiveBufferStatus(SPI_MODULE_ID index)
static void DRV_TMR3_Open(void)
void PLIB_SPI_ReceiverOverflowClear(SPI_MODULE_ID index)
void SYS_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
static void Init_FSK(void)
bool DRV_TMR0_Start(void)
static uint16_t PIB_Status
void DRV_PMP0_Write(uint8_t data)
void PLIB_SPI_ErrorInterruptDisable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
bool PLIB_PORTS_ExistsPortsRead(PORTS_MODULE_ID index)
bool PLIB_DMA_SuspendIsEnabled(DMA_MODULE_ID index)
bool DRV_IC_BufferIsEmpty(DRV_HANDLE handle)
void PLIB_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION inputFunction, PORTS_REMAP_INPUT_PIN remapInputPin)
bool PLIB_DMA_ExistsChannelXAbortIRQ(DMA_MODULE_ID index)
SYS_MODULE_OBJ DRV_USART0_Initialize(void)
DRV_SPI_PROTOCOL_TYPE spiProtocolType
bool PLIB_DMA_ExistsAbortTransfer(DMA_MODULE_ID index)
bool PLIB_USART_TransmitterBufferIsFull(USART_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR3_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_SPI_BufferWrite16bit(SPI_MODULE_ID index, uint16_t data)
void PLIB_DMA_ChannelXCellSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t CellSize)
size_t DRV_USART_BufferProcessedSizeGet(DRV_USART_BUFFER_HANDLE bufferHandle)
static void DRV_TMR2_Close(void)
SPI_FRAME_PULSE_WIDTH framePulseWidth
bool PLIB_SPI_ExistsFrameSyncPulseDirection(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulsePolarity(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceFlagClear(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
DRV_USART_BAUD_SET_RESULT DRV_USART0_BaudSet(uint32_t baud)
void SYS_PORTS_ChangeNotificationPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
static void qqqqinitialise(int ii)
void PLIB_DMA_ChannelXPatternIgnoreByteEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
size_t SYS_DMA_ChannelSourceTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_SPI_FIFOInterruptModeSelect(SPI_MODULE_ID index, SPI_FIFO_INTERRUPT mode)
void PLIB_USART_Enable(USART_MODULE_ID index)
void DRV_TMR2_Initialize(void)
void PLIB_DMA_CRCAppendModeDisable(DMA_MODULE_ID index)
void SYS_PORTS_DirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_USART_ExistsEnable(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortInIdle(PORTS_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePullUpPerPort(PORTS_MODULE_ID index)
DMA_CRC_TYPE PLIB_DMA_CRCTypeGet(DMA_MODULE_ID index)
void SYS_PORTS_PinDirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_ChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_DMA_ChannelXNullWriteModeIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_ChangeNoticePullDownPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_PORTS_ExistsPinMode(PORTS_MODULE_ID index)
static int qqqstructzzopen
SYS_MODULE_OBJ DRV_USART_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool PLIB_SPI_ExistsFrameSyncPulseEdge(SPI_MODULE_ID index)
void PLIB_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
DRV_USART_CLIENT_STATUS DRV_USART0_ClientStatus(void)
void DRV_TMR4_Initialize(void)
void PLIB_SPI_AudioCommunicationWidthSelect(SPI_MODULE_ID index, SPI_AUDIO_COMMUNICATION_WIDTH mode)
DRV_TMR_OPERATION_MODE DRV_TMR0_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void SYS_PORTS_ChangeNotificationInIdleModeEnable(PORTS_MODULE_ID index)
DMA_TRANSFER_MODE PLIB_DMA_ChannelXOperatingTransferModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsEnableControl(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXChainEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_BaudRateSet(SPI_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
bool PLIB_USART_ExistsReceiverAddressDetect(USART_MODULE_ID index)
bool DRV_TMR_ClockSet(DRV_HANDLE handle, DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE preScale)
void PLIB_PORTS_CnPinsDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void SYS_PORTS_PinPullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void APP_Initialize(void)
void PLIB_DMA_StopInIdleEnable(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_PRIORITY channelPriority)
void SYS_DMA_ChannelCRCSet(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OPERATION_MODE_CRC crc)
void SYS_DMA_ChannelTransferEventHandlerSet(SYS_DMA_CHANNEL_HANDLE handle, const SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER eventHandler, const uintptr_t contextHandle)
void DRV_TMR0_PeriodValueSet(uint32_t value)
uint32_t DRV_TMR3_CounterFrequencyGet(void)
bool PLIB_DMA_ExistsCRCWriteByteOrder(DMA_MODULE_ID index)
uint32_t DRV_TMR1_CounterFrequencyGet(void)
static unsigned char qqqzzglobflag
static void DRV_TMR2_DeInitialize(void)
bool PLIB_SPI_ExistsFramedCommunication(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXINTSource(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiver(USART_MODULE_ID index)
bool PLIB_USART_ExistsHandshakeMode(USART_MODULE_ID index)
bool PLIB_SPI_Exists16bitBuffer(SPI_MODULE_ID index)
void PLIB_SPI_AudioTransmitModeSelect(SPI_MODULE_ID index, SPI_AUDIO_TRANSMIT_MODE mode)
bool PLIB_USART_ExistsStopInIdle(USART_MODULE_ID index)
bool PLIB_SPI_ExistsTransmitBufferEmptyStatus(SPI_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART_LineControlSet(const DRV_HANDLE client, const DRV_USART_LINE_CONTROL lineControl)
void PLIB_DMA_CRCDisable(DMA_MODULE_ID index)
void DRV_TMR3_PeriodValueSet(uint32_t value)
uint32_t DRV_TMR_AlarmHasElapsed(DRV_HANDLE handle)
void PLIB_USART_HandshakeModeSelect(USART_MODULE_ID index, USART_HANDSHAKE_MODE handshakeConfig)
bool PLIB_SPI_ExistsAudioCommunicationWidth(SPI_MODULE_ID index)
DRV_SPI_BUFFER_TYPE bufferType
uint16_t DRV_IC0_Capture16BitDataRead(void)
bool PLIB_SPI_ExistsFIFOControl(SPI_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_USART_ExistsRunInOverflow(USART_MODULE_ID index)
void DRV_TMR_AlarmEnable(DRV_HANDLE handle, bool enable)
bool PLIB_PORTS_ExistsRemapInput(PORTS_MODULE_ID index)
void PLIB_DMA_CRCByteOrderSelect(DMA_MODULE_ID index, DMA_CRC_BYTE_ORDER byteOrder)
DRV_TMR_OPERATION_MODE DRV_TMR1_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool PLIB_USART_ExistsLoopback(USART_MODULE_ID index)
bool PLIB_SPI_FIFOShiftRegisterIsEmpty(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DMA_ChannelEnable(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_DMA_ExistsChannelXDestinationPointer(DMA_MODULE_ID index)
SYS_DMA_CHANNEL_CHAIN_PRIO
void PLIB_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
bool PLIB_USART_ExistsTransmitterBufferFullStatus(USART_MODULE_ID index)
PORTS_CHANGE_NOTICE_METHOD PLIB_PORTS_ChannelChangeNoticeMethodGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
DRV_TMR_OPERATION_MODE DRV_TMR2_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool PLIB_USART_RunInSleepModeIsEnabled(USART_MODULE_ID index)
bool DRV_TMR0_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
DMA_CHANNEL_ADDRESSING_MODE PLIB_DMA_ChannelXAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ReceiverHasOverflowed(SPI_MODULE_ID index)
TMR_PRESCALE DRV_TMR1_PrescalerGet(void)
bool PLIB_DMA_ChannelXChainIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsOperationMode(USART_MODULE_ID index)
void PLIB_USART_TransmitterByteSend(USART_MODULE_ID index, int8_t data)
void PLIB_PORTS_ChangeNoticeInIdleDisable(PORTS_MODULE_ID index)
void PLIB_USART_AddressMaskSet(USART_MODULE_ID index, uint8_t mask)
DRV_USART_ERROR DRV_USART_ErrorGet(const DRV_HANDLE client)
void SYS_PORTS_PinPullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
static int statusst_58zqzqzq(int qqqi)
uint32_t DRV_TMR2_CounterValueGet(void)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void PLIB_DMA_ChannelXPatternDataSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t patternData)
bool PLIB_PORTS_PinChangeNoticeEdgeIsEnabled(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_CHANGE_NOTICE_EDGE cnEdgeType)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite2(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
bool PLIB_USART_ReceiverFramingErrorHasOccurred(USART_MODULE_ID index)
uint32_t DRV_TMR3_PeriodValueGet(void)
bool PLIB_SPI_ExistsBaudRateClock(SPI_MODULE_ID index)
void DRV_TMR_Deinitialize(SYS_MODULE_OBJ object)
bool PLIB_USART_TransmitterBreakSendIsComplete(USART_MODULE_ID index)
void SYS_PORTS_ChangeNotificationInIdleModeDisable(PORTS_MODULE_ID index)
void PLIB_DMA_SuspendEnable(DMA_MODULE_ID index)
void PLIB_USART_RunInOverflowDisable(USART_MODULE_ID index)
uint8_t Get_CRC_Value(void)
void DRV_PMP0_Initialize(void)
void PLIB_DMA_ChannelXSourceAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_SOURCE_ADDRESSING_MODE sourceAddressMode)
bool DRV_TMR_GateModeSet(DRV_HANDLE handle)
void DRV_TMR_CounterValueSet(DRV_HANDLE handle, uint32_t counterPeriod)
uint32_t SYS_DMA_ChannelCRCGet(void)
void PLIB_DMA_ChannelXPatternIgnoreByteDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_TMR_CLIENT_STATUS DRV_TMR3_ClientStatus(void)
void PLIB_SPI_BufferClear(SPI_MODULE_ID index)
PORTS_DATA_TYPE PLIB_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void DRV_TMR1_StopInIdleEnable(void)
void PLIB_USART_BaudSetAndEnable(USART_MODULE_ID index, uint32_t systemClock, uint32_t baud)
void PLIB_DMA_CRCBitOrderSelect(DMA_MODULE_ID index, DMA_CRC_BIT_ORDER bitOrder)
void PLIB_PORTS_ChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_DMA_ChannelXPatternLengthSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_PATTERN_LENGTH patternLen)
void DRV_TMR_Tasks(SYS_MODULE_OBJ object)
void qqqtotalupload(void)
void PLIB_DMA_CRCWriteByteOrderMaintain(DMA_MODULE_ID index)
bool PLIB_DMA_IsBusy(DMA_MODULE_ID index)
void DRV_PMP0_ModeConfig(void)
void PLIB_PORTS_PinChangeNoticePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_ReceiverAddressAutoDetectEnable(USART_MODULE_ID index, int8_t Mask)
bool DRV_SPIn_TransmitterBufferIsFull(void)
void PLIB_PORTS_PinChangeNoticePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
unsigned int DRV_USART0_ReceiverBufferSizeGet(void)
uint32_t DRV_TMR1_CounterValueGet(void)
SPI_FRAME_PULSE_EDGE framePulseEdge
bool PLIB_DMA_ExistsChannelXChainEnbl(DMA_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterEnable(USART_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR4_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_SPI_FrameSyncPulseEdgeSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_EDGE edge)
void PLIB_PORTS_ChannelChangeNoticePullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_SPI_ExistsClockPolarity(SPI_MODULE_ID index)
void SYS_DMA_ChannelTransferSet(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
bool PLIB_USART_ExistsReceiverDataAvailableStatus(USART_MODULE_ID index)
static const uint8_t Xmit11[312]
static void DRV_TMR1_Tasks(void)
SYS_DMA_CHANNEL_IGNORE_MATCH
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelPriorityGet(DMA_MODULE_ID index)
SYS_STATUS DRV_TMR_Status(SYS_MODULE_OBJ object)
SYS_MODULE_OBJ DRV_SPI_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void PLIB_DMA_ChannelXINTSourceEnable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
static SYS_STATUS DRV_TMR2_Status(void)
uint8_t DRV_USART0_ReadByte(void)
uint8_t PLIB_DMA_ChannelBitsGet(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXDestinationSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t destinationSize)
size_t DRV_USART_Write(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
void * PLIB_USART_TransmitterAddressGet(USART_MODULE_ID index)
bool PLIB_DMA_LastBusAccessIsWrite(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelX(DMA_MODULE_ID index)
bool DRV_TMR3_Start(void)
DRV_HANDLE DRV_IC_Start(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT intent)
DMA_CHANNEL_DATA_SIZE PLIB_DMA_ChannelXDataSizeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_PinDisable(SPI_MODULE_ID index, SPI_PIN pin)
void PLIB_SPI_FIFODisable(SPI_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR2_OperationModeGet(void)
bool DRV_USART0_TransmitBufferIsFull(void)
uintptr_t DRV_USART_BUFFER_HANDLE
uintptr_t DRV_USART_BUFFER_HANDLE
static const uint8_t Xmit00[168]
void SYS_PORTS_InterruptEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_INTERRUPT_TYPE pinInterruptType)
int8_t PLIB_USART_ReceiverByteReceive(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXEvent(DMA_MODULE_ID index)
void DRV_TMR2_CounterValueSet(uint32_t value)
bool PLIB_DMA_ExistsChannelXDestinationStartAddress(DMA_MODULE_ID index)
bool PLIB_USART_ReceiverAddressIsReceived(USART_MODULE_ID index)
bool DRV_TMR4_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_DMA_CRCPolynomialLengthSet(DMA_MODULE_ID index, uint8_t polyLength)
void PLIB_PORTS_ChannelSlewRateSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK channelMask, PORTS_PIN_SLEW_RATE slewRate)
unsigned int DRV_USART_ReceiverBufferSizeGet(const DRV_HANDLE handle)
void PLIB_DMA_BusyActiveReset(DMA_MODULE_ID index)
bool PLIB_SPI_TransmitBufferIsEmpty(SPI_MODULE_ID index)
void PLIB_SPI_OutputDataPhaseSelect(SPI_MODULE_ID index, SPI_OUTPUT_DATA_PHASE phase)
bool PLIB_PORTS_ExistsChangeNoticePullUp(PORTS_MODULE_ID index)
#define statusst_58zzopen
void SYS_PORTS_ChangeNotificationGlobalDisable(PORTS_MODULE_ID index)
void PLIB_USART_TransmitterDisable(USART_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
static int qqqqbmselwidth
void PLIB_USART_BaudRateAutoDetectEnable(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticeEdgeStatus(PORTS_MODULE_ID index)
void qqpopulate_array_fcn_ptrQQ(int x, ldra_void_function y, ldra_void_function z)
bool PLIB_SPI_ExistsBuffer(SPI_MODULE_ID index)
CLK_BUSES_PERIPHERAL spiClk
SYS_MODULE_OBJ DRV_TMR_Initialize(const SYS_MODULE_INDEX drvIndex, const SYS_MODULE_INIT *const init)
void PLIB_PORTS_ChannelChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool DRV_USART0_ReceiverBufferIsEmpty(void)
DRV_TMR_CLIENT_STATUS DRV_TMR0_ClientStatus(void)
bool PLIB_SPI_ExistsBaudRate(SPI_MODULE_ID index)
void DRV_ADC_Initialize(void)
DRV_TMR_OPERATION_MODE DRV_TMR_DividerRangeGet(DRV_HANDLE handle, DRV_TMR_DIVIDER_RANGE *pDivRange)
SYS_STATUS DRV_USART0_Status(void)
void PLIB_SPI_FrameErrorStatusClear(SPI_MODULE_ID index)
void(* DRV_USART_BYTE_EVENT_HANDLER)(const SYS_MODULE_INDEX index)
DMA_PING_PONG_MODE PLIB_DMA_ChannelXPingPongModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR3_DeInitialize(void)
void DRV_TMR2_PeriodValueSet(uint32_t value)
void DRV_TMR0_Initialize(void)
void DRV_USART_BufferEventHandlerSet(const DRV_HANDLE handle, const DRV_USART_BUFFER_EVENT_HANDLER eventHandler, const uintptr_t context)
bool DRV_TMR_AlarmRegister(DRV_HANDLE handle, uint32_t divider, bool isPeriodic, uintptr_t context, DRV_TMR_CALLBACK callBack)
bool PLIB_PORTS_ExistsPortsDirection(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsReceiverOverflow(SPI_MODULE_ID index)
void PLIB_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION outputFunction, PORTS_REMAP_OUTPUT_PIN remapOutputPin)
void DRV_TMR3_StopInIdleDisable(void)
void PLIB_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
void PLIB_USART_LoopbackEnable(USART_MODULE_ID index)
SYS_ERROR_LEVEL SYS_DEBUG_ErrorLevelGet(void)
SPI_COMMUNICATION_WIDTH commWidth
DRV_USART_TRANSFER_STATUS
void PLIB_PORTS_PinModePerPortSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_MODE mode)
void PLIB_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void DRV_TMR3_CounterClear(void)
void DRV_TMR_CounterClear(DRV_HANDLE handle)
bool PLIB_USART_ExistsBaudRateHigh(USART_MODULE_ID index)
uint16_t PLIB_SPI_BufferRead16bit(SPI_MODULE_ID index)
bool DRV_TMR3_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_DMA_CRCTypeSet(DMA_MODULE_ID index, DMA_CRC_TYPE CRCType)
bool PLIB_USART_ModuleIsBusy(USART_MODULE_ID index)
void PLIB_PORTS_PinDirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint8_t PLIB_SPI_BufferRead(SPI_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR3_OperationModeGet(void)
void PLIB_USART_AddressSet(USART_MODULE_ID index, uint8_t address)
bool PLIB_DMA_ExistsCRCAppendMode(DMA_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead2(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
unsigned int DRV_USART0_TransmitBufferSizeGet(void)
bool PLIB_DMA_ChannelXINTSourceIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
uint8_t Fifo_Get(TFifo *ptrFifo)
bool DRV_TMR_Start(DRV_HANDLE handle)
bool DRV_TMR_GateModeClear(DRV_HANDLE handle)
bool PLIB_PORTS_ExistsLatchRead(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternIgnoreByte(DMA_MODULE_ID index)
void PLIB_DMA_CRCWriteByteOrderAlter(DMA_MODULE_ID index)
static SYS_STATUS DRV_TMR3_Status(void)
void SYS_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION function, PORTS_REMAP_INPUT_PIN remapPin)
bool PLIB_USART_WakeOnStartIsEnabled(USART_MODULE_ID index)
void SYS_DEBUG_ErrorLevelSet(SYS_ERROR_LEVEL level)
void SYS_DMA_ChannelSetup(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OP_MODE modeEnable, DMA_TRIGGER_SOURCE eventSrc)
void SYS_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
void PLIB_SPI_FrameSyncPulsePolaritySelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_POLARITY polarity)
void PLIB_DMA_ChannelXChainToLower(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_SPI_BUFFER_EVENT DRV_SPI_BufferStatus(DRV_SPI_BUFFER_HANDLE bufferHandle)
void DRV_TMR2_CounterClear(void)
void SYS_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_IsEnabled(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXBufferedDataIsWritten(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsReceiveFIFOStatus(SPI_MODULE_ID index)
void DRV_USART0_Deinitialize(void)
void DRV_USART0_TasksTransmit(void)
DRV_USART_TRANSFER_STATUS DRV_USART0_TransferStatus(void)
struct _DRV_SPI_CLIENT_DATA DRV_SPI_CLIENT_DATA
void SYS_PORTS_Initialize()
uint16_t DRV_IC_Capture16BitDataRead(DRV_HANDLE handle)
uint8_t PLIB_USART_AddressMaskGet(USART_MODULE_ID index)
void PLIB_DMA_ChannelXReloadDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_Enable(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelModeSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK modeMask, PORTS_PIN_MODE mode)
void SYS_DMA_ChannelSuspend(SYS_DMA_CHANNEL_HANDLE handle)
void SYS_PORTS_ChangeNotificationGlobalEnable(PORTS_MODULE_ID index)
void PLIB_USART_Disable(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
void PLIB_USART_WakeOnStartDisable(USART_MODULE_ID index)
void PLIB_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool DRV_USART_TransmitBufferIsFull(const DRV_HANDLE handle)
static void qqqbitmapreset(qqnull_params)
void SYS_DMA_ChannelForceAbort(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_RunInSleepModeEnable(USART_MODULE_ID index)
TMR_PRESCALE DRV_TMR2_PrescalerGet(void)
bool PLIB_USART_ExistsReceiverFramingErrorStatus(USART_MODULE_ID index)
bool PLIB_SPI_ExistsBusStatus(SPI_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXPeripheralAddressGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_USART_Close(const DRV_HANDLE handle)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
bool PLIB_DMA_ExistsChannelXSourceSize(DMA_MODULE_ID index)
void DRV_USART_TasksError(SYS_MODULE_OBJ object)
void PLIB_DMA_ChannelXReloadEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsChangeNoticeInIdle(PORTS_MODULE_ID index)
void(* ldra_void_function)()
static void qqoutput3(FILEPOINT char *s, int i, int j, int k)
void Prepare_Dwn_Msg(uint8_t Identifier, uint8_t Cmd, uint8_t Msg_Length)
void PLIB_USART_InitializeModeGeneral(USART_MODULE_ID index, bool autobaud, bool loopBackMode, bool wakeFromSleep, bool irdaMode, bool stopInIdle)
static int statusst_58zscanf(char *qqscan_str)
void PLIB_USART_RunInOverflowEnable(USART_MODULE_ID index)
TMR_PRESCALE DRV_TMR_PrescalerGet(DRV_HANDLE handle)
bool PLIB_SPI_ExistsFIFOCount(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsTransmitUnderRunStatus(SPI_MODULE_ID index)
void DRV_TMR2_StopInIdleEnable(void)
uint32_t PLIB_DMA_CRCXOREnableGet(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsBusy(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeEdgeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void PLIB_DMA_StopInIdleDisable(DMA_MODULE_ID index)
void PLIB_USART_ReceiverIdleStateLowDisable(USART_MODULE_ID index)
void PLIB_SPI_TransmitUnderRunStatusClear(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXTrigger(DMA_MODULE_ID index)
void PLIB_PORTS_DirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void DRV_USART_TasksReceive(SYS_MODULE_OBJ object)
void SYS_PORTS_ChangeNotificationEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum, SYS_PORTS_PULLUP_PULLDOWN_STATUS value)
bool PLIB_DMA_ExistsEnableControl(DMA_MODULE_ID index)
SYS_STATUS SYS_DEBUG_Status(SYS_MODULE_OBJ object)
bool PLIB_PORTS_ExistsChangeNotice(PORTS_MODULE_ID index)
uint32_t DRV_TMR2_PeriodValueGet(void)
void SYS_DEBUG_Print(const char *format,...)
bool PLIB_DMA_ExistsChannelXINTSourceFlag(DMA_MODULE_ID index)
static void DRV_TMR4_Close(void)
DRV_TMR_CLIENT_STATUS DRV_TMR1_ClientStatus(void)
uint16_t PLIB_DMA_ChannelXPatternDataGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_DMA_ChannelXPeripheralAddressSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t peripheraladdress)
void PLIB_DMA_ChannelXNullWriteModeDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_CnPinsEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void PLIB_SPI_AudioProtocolEnable(SPI_MODULE_ID index)
bool PLIB_USART_ExistsBaudRateAutoDetect(USART_MODULE_ID index)
void SYS_DMA_ChannelResume(SYS_DMA_CHANNEL_HANDLE handle)
void DRV_TMR1_CounterClear(void)
DRV_HANDLE DRV_SPI_Open(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT ioIntent)
PORTS_DATA_TYPE SYS_PORTS_LatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_ChannelXTriggerIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
DRV_USART_CLIENT_STATUS DRV_USART_ClientStatus(DRV_HANDLE handle)
void PLIB_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
void PLIB_DMA_ChannelXBusyActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXDisabled(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortTurnOn(PORTS_MODULE_ID index)
static void DRV_TMR0_Tasks(void)
void PLIB_USART_RunInSleepModeDisable(USART_MODULE_ID index)
bool PLIB_USART_BaudRateAutoDetectIsComplete(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeEnable(PORTS_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_StartTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsBaudRate(USART_MODULE_ID index)
void DRV_TMR4_CounterClear(void)
DRV_HANDLE DRV_TMR_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT intent)
uint8_t DRV_USART_ReadByte(const DRV_HANDLE handle)
static void Send_Mark(void)
uint32_t DRV_TMR1_PeriodValueGet(void)
void SYS_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_IC0_Initialize(void)
void DRV_TMR3_StopInIdleEnable(void)
bool PLIB_DMA_ExistsCRCData(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePullDownPerPort(PORTS_MODULE_ID index)
void PLIB_SPI_Enable(SPI_MODULE_ID index)
bool DRV_TMR2_Start(void)
bool PLIB_SPI_ExistsAudioTransmitMode(SPI_MODULE_ID index)
static void DRV_TMR3_Tasks(void)
void PLIB_DMA_ChannelPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL_PRIORITY channelPriority)
void PLIB_USART_TransmitterEnable(USART_MODULE_ID index)
SPI_INPUT_SAMPLING_PHASE inputSamplePhase
DMA_SOURCE_ADDRESSING_MODE PLIB_DMA_ChannelXSourceAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR4_PeriodValueSet(uint32_t value)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
DMA_CHANNEL_TRANSFER_DIRECTION PLIB_DMA_ChannelXTransferDirectionGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
size_t DRV_USART_Read(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
void PLIB_DMA_CRCDataWrite(DMA_MODULE_ID index, uint32_t DMACRCdata)
static void DRV_TMR1_DeInitialize(void)
DRV_USART_BUFFER_RESULT DRV_USART_BufferRemove(DRV_USART_BUFFER_HANDLE bufferHandle)
bool PLIB_SPI_ReadDataIsSignExtended(SPI_MODULE_ID index)
void SYS_DMA_ChannelRelease(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_DMA_BusyActiveSet(DMA_MODULE_ID index)
void PLIB_USART_IrDADisable(USART_MODULE_ID index)
void SYS_DMA_ChannelSetupMatchAbortMode(SYS_DMA_CHANNEL_HANDLE handle, uint16_t pattern, DMA_PATTERN_LENGTH length, SYS_DMA_CHANNEL_IGNORE_MATCH ignore, uint8_t ignorePattern)
bool PLIB_DMA_ExistsSuspend(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXTransferCountSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t transferCount)
bool PLIB_SPI_ExistsStopInIdleControl(SPI_MODULE_ID index)
uint8_t Calc_CRC_Array(uint16_t Count, const uint8_t Bytes [])
static void DRV_TMR0_Open(void)
SYS_MODULE_OBJ DRV_IC_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool PLIB_DMA_ExistsChannelXSourceStartAddress(DMA_MODULE_ID index)
void PLIB_SPI_AudioErrorDisable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
void SYS_DMA_Resume(void)
static void DRV_TMR2_Tasks(void)
static void DRV_TMR1_Close(void)
DMA_CHANNEL PLIB_DMA_CRCChannelGet(DMA_MODULE_ID index)
bool DRV_TMR4_Start(void)
bool PLIB_DMA_ExistsChannelXDestinationSize(DMA_MODULE_ID index)
bool DRV_TMR2_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
uintptr_t DRV_SPI_BUFFER_HANDLE
void PLIB_PORTS_ChangeNoticeInIdlePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
uint8_t PLIB_SPI_FIFOCountGet(SPI_MODULE_ID index, SPI_FIFO_TYPE type)
bool PLIB_USART_ExistsTransmitterBreak(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsPinModePerPort(PORTS_MODULE_ID index)
void SYS_DMA_ChannelAbortEventSet(SYS_DMA_CHANNEL_HANDLE handle, DMA_TRIGGER_SOURCE eventSrc)
uint32_t PLIB_DMA_CRCDataRead(DMA_MODULE_ID index)
bool DRV_ADC_SamplesAvailable(uint8_t bufIndex)
void PLIB_PORTS_AnPinsModeSelect(PORTS_MODULE_ID index, PORTS_AN_PIN anPins, PORTS_PIN_MODE mode)
SPI_AUDIO_TRANSMIT_MODE audioTransmitMode
bool PLIB_PORTS_ExistsChannelChangeNoticeMethod(PORTS_MODULE_ID index)
void Set_Status(uint8_t bitposn)
void PLIB_SPI_SlaveEnable(SPI_MODULE_ID index)
static void qqoutput4(FILEPOINT char *s, int i, int j, int k, int l)
void PLIB_DMA_ChannelXDataSizeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_DATA_SIZE channelDataSize)
uint32_t DRV_TMR4_CounterValueGet(void)
bool PLIB_USART_ExistsWakeOnStart(USART_MODULE_ID index)
void PLIB_USART_ReceiverAddressAutoDetectDisable(USART_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseCounterSelect(SPI_MODULE_ID index, SPI_FRAME_SYNC_PULSE pulse)
void DRV_USART_BufferAddWrite(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *bufferHandle, void *buffer, const size_t size)
PORTS_PIN_SLEW_RATE PLIB_PORTS_PinSlewRateGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXPatternIgnoreSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint8_t pattern)
uintptr_t DRV_SPI_BUFFER_HANDLE
bool PLIB_SPI_ExistsInputSamplePhase(SPI_MODULE_ID index)
void(* DRV_USART_BUFFER_EVENT_HANDLER)(DRV_USART_BUFFER_EVENT event, DRV_USART_BUFFER_HANDLE bufferHandle, uintptr_t context)
void PLIB_DMA_ChannelXNullWriteModeEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_InitializeOperation(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE receiveInterruptMode, USART_TRANSMIT_INTR_MODE transmitInterruptMode, USART_OPERATION_MODE operationMode)
uint16_t PLIB_DMA_ChannelXCellSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool DRV_TMR_AlarmDisable(DRV_HANDLE handle)
bool PLIB_USART_ExistsIrDA(USART_MODULE_ID index)
static void qqoutput2(FILEPOINT char *s, int i, int j)
SPI_AUDIO_PROTOCOL audioProtocolMode
bool PLIB_USART_ExistsReceiverIdleStatus(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeInIdlePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
DRV_SPI_CLOCK_MODE clockMode
void PLIB_PORTS_ChangeNoticeDisable(PORTS_MODULE_ID index)
void Prepare_Return_B(uint8_t byt [])
DRV_TMR_CLIENT_STATUS DRV_TMR4_ClientStatus(void)
#define DRV_IC_Close(handle)
void PLIB_DMA_ChannelXDisabledDisablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsAudioProtocolMode(SPI_MODULE_ID index)
void PLIB_SPI_PinEnable(SPI_MODULE_ID index, SPI_PIN pin)
static int statusst_58zqqzqz(qqnull_params)
void DRV_USART_TasksTransmit(SYS_MODULE_OBJ object)
SYS_MODULE_OBJ SYS_DMA_Initialize(const SYS_MODULE_INIT *const init)
bool PLIB_USART_ExistsBRGClockSourceSelect(USART_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeMethodSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod)
void PLIB_USART_BaudRateHighDisable(USART_MODULE_ID index)
uintptr_t SYS_DMA_CHANNEL_HANDLE
void SYS_DMA_Tasks(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
void PLIB_DMA_ChannelXSourceSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t sourceSize)
void PLIB_USART_StopInIdleDisable(USART_MODULE_ID index)
DRV_USART_ERROR DRV_USART0_ErrorGet(void)
void DRV_TMR_AlarmDeregister(DRV_HANDLE handle)
void Calc_CRC(uint16_t nbits, uint8_t thebits)
uint32_t DRV_TMR0_CounterValueGet(void)
void DRV_SPI_Tasks(SYS_MODULE_OBJ object)
bool PLIB_SPI_ReceiverFIFOIsEmpty(SPI_MODULE_ID index)
PORTS_DATA_TYPE SYS_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_PORTS_ChangeNoticePullDownPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ExistsAudioProtocolControl(SPI_MODULE_ID index)
uint8_t PLIB_DMA_ChannelXPatternIgnoreGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXChainDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
static void qqqupload(qqnull_params)
void SYS_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
void PLIB_SPI_StopInIdleDisable(SPI_MODULE_ID index)
TMR_PRESCALE DRV_TMR0_PrescalerGet(void)
bool PLIB_SPI_ReceiverBufferIsFull(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXTransferDirectionSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection)
void PLIB_DMA_Disable(DMA_MODULE_ID index)
uint32_t DRV_TMR_CounterFrequencyGet(DRV_HANDLE handle)
void PLIB_SPI_AudioErrorEnable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
DRV_USART_LINE_CONTROL_SET_RESULT
bool PLIB_DMA_ExistsChannelXSourcePointer(DMA_MODULE_ID index)
INT_SOURCE rxInterruptSource
#define DRV_IC_Open(drvIndex, intent)
uint16_t PLIB_DMA_ChannelXStartAddressOffsetGet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_ADDRESS_OFFSET_TYPE offset)
void PLIB_DMA_ChannelXChainToHigher(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_ChannelChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_SPI_ExistsFrameSyncPulseCounter(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXCellSize(DMA_MODULE_ID index)
bool PLIB_SPI_IsBusy(SPI_MODULE_ID index)
bool PLIB_DMA_ChannelXIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsTransmitter(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePerPortTurnOn(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void SYS_PORTS_ChangeNotificationPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_SPI_FrameSyncPulseDirectionSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_DIRECTION direction)
bool PLIB_USART_ExistsModuleBusyStatus(USART_MODULE_ID index)
bool PLIB_USART_ReceiverParityErrorHasOccurred(USART_MODULE_ID index)
void DRV_TMR1_StopInIdleDisable(void)
void PLIB_DMA_ChannelXDestinationAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode)
bool SYS_PORTS_PinRead(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_ADC1_Close(void)
bool PLIB_USART_ExistsTransmitterInterruptMode(USART_MODULE_ID index)
void PLIB_DMA_ChannelXTriggerDisable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void PLIB_SPI_BaudRateClockSelect(SPI_MODULE_ID index, SPI_BAUD_RATE_CLOCK type)
bool PLIB_PORTS_PinChangeNoticeEdgeHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ExistsFIFOShiftRegisterEmptyStatus(SPI_MODULE_ID index)
void PLIB_USART_Transmitter9BitsSend(USART_MODULE_ID index, int8_t data, bool Bit9th)
bool PLIB_DMA_ExistsChannelXChain(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelBits(DMA_MODULE_ID index)
void SYS_DEBUG_Message(const char *message)
INT_SOURCE errInterruptSource
void PLIB_USART_LineControlModeSelect(USART_MODULE_ID index, USART_LINECONTROL_MODE dataFlowConfig)
void PLIB_SPI_AudioProtocolDisable(SPI_MODULE_ID index)
static void DRV_TMR2_Open(void)
bool PLIB_DMA_ExistsChannelXPatternLength(DMA_MODULE_ID index)
void PLIB_SPI_BufferWrite32bit(SPI_MODULE_ID index, uint32_t data)
ldra_void_function qqqaccumreset[QQQnumfil]
bool PLIB_USART_ExistsRunInSleepMode(USART_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXTransferCountGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsReceiverAddress(USART_MODULE_ID index)
void SYS_DMA_ChannelForceStart(SYS_DMA_CHANNEL_HANDLE handle)
uint32_t DRV_TMR2_CounterFrequencyGet(void)
uint32_t DRV_TMR_CounterValueGet(DRV_HANDLE handle)
void PLIB_DMA_ChannelXTriggerEnable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
uint32_t PLIB_SPI_BufferRead32bit(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXStartAddressOffsetSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t address, DMA_ADDRESS_OFFSET_TYPE offset)
size_t DRV_USART_BufferCompletedBytesGet(DRV_USART_BUFFER_HANDLE bufferHandle)
bool PLIB_DMA_ChannelXINTSourceFlagGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void * PLIB_SPI_BufferAddressGet(SPI_MODULE_ID index)
void DRV_USART0_TasksReceive(void)
bool PLIB_DMA_ExistsCRCBitOrder(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceDisable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_DMA_ExistsChannelXPriority(DMA_MODULE_ID index)
DRV_USART_BAUD_SET_RESULT
DRV_TMR_CLIENT_STATUS DRV_TMR_ClientStatus(DRV_HANDLE handle)
bool PLIB_USART_ExistsReceiverAddressAutoDetect(USART_MODULE_ID index)
bool PLIB_SPI_ExistsReadDataSignStatus(SPI_MODULE_ID index)
void SYS_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
DRV_TMR_CLIENT_STATUS DRV_TMR2_ClientStatus(void)
uint32_t PLIB_DMA_ChannelXSourceStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
PORTS_DATA_TYPE PLIB_PORTS_ReadLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_USART_LoopbackDisable(USART_MODULE_ID index)
void DRV_TMR4_StopInIdleEnable(void)
uint8_t DRV_PMP0_Read(void)
DRV_SPI_TASK_MODE taskMode
void PLIB_DMA_ChannelXINTSourceFlagSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
DRV_USART_BAUD_SET_RESULT DRV_USART_BaudSet(const DRV_HANDLE client, uint32_t baud)
void PLIB_PORTS_ChangeNoticePerPortTurnOff(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void SYS_DMA_ChannelDisable(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_ReceiverInterruptModeSelect(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE interruptMode)
bool PLIB_DMA_ExistsCRCXOREnable(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_USART_ExistsReceiverIdleStateLowEnable(USART_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterIdleIsLow(USART_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXDestinationSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void DRV_TMR_Stop(DRV_HANDLE handle)
bool DRV_TMR1_Start(void)
void PLIB_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_PORTS_ExistsRemapOutput(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsMasterControl(SPI_MODULE_ID index)
void DRV_TMR1_Initialize(void)
uint8_t PLIB_DMA_CRCPolynomialLengthGet(DMA_MODULE_ID index)
void PLIB_SPI_FIFOEnable(SPI_MODULE_ID index)
uint32_t DRV_IC0_Capture32BitDataRead(void)
void PLIB_DMA_ChannelXOperatingTransferModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRANSFER_MODE channeltransferMode)
void DRV_TMR_Close(DRV_HANDLE handle)
void DRV_USART0_TasksError(void)
void SYS_DMA_ChannelTransferAdd(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
bool PLIB_DMA_ExistsLastBusAccess(DMA_MODULE_ID index)
static void qqbmsoutput(FILEPOINT char *s, unsigned int i)
void PLIB_USART_TransmitterInterruptModeSelect(USART_MODULE_ID index, USART_TRANSMIT_INTR_MODE fifolevel)
void DRV_PMP0_TimingSet(PMP_DATA_WAIT_STATES dataWait, PMP_STROBE_WAIT_STATES strobeWait, PMP_DATA_HOLD_STATES dataHold)
void PLIB_DMA_ChannelXAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_ADDRESSING_MODE channelAddressMode)
bool PLIB_DMA_ExistsCRCByteOrder(DMA_MODULE_ID index)
void PLIB_DMA_CRCEnable(DMA_MODULE_ID index)
static SYS_STATUS DRV_TMR0_Status(void)
bool DRV_USART_ReceiverBufferIsEmpty(const DRV_HANDLE handle)
bool PLIB_DMA_ExistsChannelXBusy(DMA_MODULE_ID index)
void PLIB_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_CommunicationWidthSelect(SPI_MODULE_ID index, SPI_COMMUNICATION_WIDTH width)
bool PLIB_DMA_ChannelXReloadIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_MasterEnable(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXDisabledEnablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_USART_ByteTransmitCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
bool PLIB_DMA_ChannelXEventIsDetected(DMA_MODULE_ID index, DMA_CHANNEL channel)
SPI_FRAME_SYNC_PULSE frameSyncPulse
uint32_t PLIB_USART_BaudRateGet(USART_MODULE_ID index, int32_t clockFrequency)
void DRV_ADC0_Close(void)
bool PLIB_DMA_ExistsChannelXAuto(DMA_MODULE_ID index)
bool PLIB_USART_RunInOverflowIsEnabled(USART_MODULE_ID index)
void PLIB_USART_BaudRateHighSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
bool PLIB_PORTS_ChangeNoticePerPortHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_InputSamplePhaseSelect(SPI_MODULE_ID index, SPI_INPUT_SAMPLING_PHASE phase)
bool PLIB_SPI_ExistsCommunicationWidth(SPI_MODULE_ID index)
void PLIB_DMA_CRCChannelSelect(DMA_MODULE_ID index, DMA_CHANNEL channel)
TMR_PRESCALE DRV_TMR3_PrescalerGet(void)
void PLIB_USART_WakeOnStartEnable(USART_MODULE_ID index)
uint32_t DRV_TMR4_CounterFrequencyGet(void)
bool PLIB_DMA_ExistsStartTransfer(DMA_MODULE_ID index)
uint32_t DRV_IC_Capture32BitDataRead(DRV_HANDLE handle)
void DRV_TMR1_CounterValueSet(uint32_t value)
bool PLIB_SPI_ExistsTransmitBufferFullStatus(SPI_MODULE_ID index)
void SYS_PORTS_PinPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void DRV_TMR4_DeInitialize(void)
static SYS_STATUS DRV_TMR4_Status(void)
void DRV_SPI_Deinitialize(SYS_MODULE_OBJ object)
uint32_t DRV_ADC_SamplesRead(uint8_t bufIndex)
void PLIB_SPI_SlaveSelectDisable(SPI_MODULE_ID index)
static void DRV_TMR1_Open(void)
void PLIB_DMA_ChannelXStartIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQnum)
void PLIB_SPI_FramedCommunicationDisable(SPI_MODULE_ID index)
void SYS_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
static DRV_TMR_OPERATION_MODE DRV_TMR4_OperationModeGet(void)
void PLIB_DMA_CRCXOREnableSet(DMA_MODULE_ID index, uint32_t DMACRCXOREnableMask)
DRV_TMR_OPERATION_MODE DRV_TMR_OperationModeGet(DRV_HANDLE handle)